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Differential D7802 Diff 20115 stable/10/sys/dev/ixl/i40e_type.h

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stable/10/sys/dev/ixl/i40e_type.h

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#define I40E_PCI_LINK_WIDTH_2 0x20 #define I40E_PCI_LINK_WIDTH_2 0x20
#define I40E_PCI_LINK_WIDTH_4 0x40 #define I40E_PCI_LINK_WIDTH_4 0x40
#define I40E_PCI_LINK_WIDTH_8 0x80 #define I40E_PCI_LINK_WIDTH_8 0x80
#define I40E_PCI_LINK_SPEED 0xF #define I40E_PCI_LINK_SPEED 0xF
#define I40E_PCI_LINK_SPEED_2500 0x1 #define I40E_PCI_LINK_SPEED_2500 0x1
#define I40E_PCI_LINK_SPEED_5000 0x2 #define I40E_PCI_LINK_SPEED_5000 0x2
#define I40E_PCI_LINK_SPEED_8000 0x3 #define I40E_PCI_LINK_SPEED_8000 0x3
#define I40E_MDIO_STCODE 0
#define I40E_MDIO_OPCODE_ADDRESS 0
#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_PHY_COM_REG_PAGE 0x1E
#define I40E_PHY_LED_LINK_MODE_MASK 0xF0
#define I40E_PHY_LED_MANUAL_ON 0x100
#define I40E_PHY_LED_PROV_REG_1 0xC430
#define I40E_PHY_LED_MODE_MASK 0xFFFF
#define I40E_PHY_LED_MODE_ORIG 0x80000000
/* Memory types */ /* Memory types */
enum i40e_memset_type { enum i40e_memset_type {
I40E_NONDMA_MEM = 0, I40E_NONDMA_MEM = 0,
I40E_DMA_MEM I40E_DMA_MEM
}; };
/* Memcpy types */ /* Memcpy types */
enum i40e_memcpy_type { enum i40e_memcpy_type {
I40E_NONDMA_TO_NONDMA = 0, I40E_NONDMA_TO_NONDMA = 0,
I40E_NONDMA_TO_DMA, I40E_NONDMA_TO_DMA,
I40E_DMA_TO_DMA, I40E_DMA_TO_DMA,
I40E_DMA_TO_NONDMA I40E_DMA_TO_NONDMA
}; };
#define I40E_FW_API_VERSION_MINOR_X710 0x0005
/* These are structs for managing the hardware information and the operations. /* These are structs for managing the hardware information and the operations.
* The structures of function pointers are filled out at init time when we * The structures of function pointers are filled out at init time when we
* know for sure exactly which hardware we're working with. This gives us the * know for sure exactly which hardware we're working with. This gives us the
* flexibility of using the same main driver code but adapting to slightly * flexibility of using the same main driver code but adapting to slightly
* different hardware needs as new parts are developed. For this architecture, * different hardware needs as new parts are developed. For this architecture,
* the Firmware and AdminQ are intended to insulate the driver from most of the * the Firmware and AdminQ are intended to insulate the driver from most of the
* future changes, but these structures will also do part of the job. * future changes, but these structures will also do part of the job.
*/ */
enum i40e_mac_type { enum i40e_mac_type {
I40E_MAC_UNKNOWN = 0, I40E_MAC_UNKNOWN = 0,
I40E_MAC_X710, I40E_MAC_X710,
I40E_MAC_XL710, I40E_MAC_XL710,
I40E_MAC_VF, I40E_MAC_VF,
#ifdef X722_SUPPORT
I40E_MAC_X722,
I40E_MAC_X722_VF,
#endif
I40E_MAC_GENERIC, I40E_MAC_GENERIC,
}; };
enum i40e_media_type { enum i40e_media_type {
I40E_MEDIA_TYPE_UNKNOWN = 0, I40E_MEDIA_TYPE_UNKNOWN = 0,
I40E_MEDIA_TYPE_FIBER, I40E_MEDIA_TYPE_FIBER,
I40E_MEDIA_TYPE_BASET, I40E_MEDIA_TYPE_BASET,
I40E_MEDIA_TYPE_BACKPLANE, I40E_MEDIA_TYPE_BACKPLANE,
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}; };
struct i40e_phy_info { struct i40e_phy_info {
struct i40e_link_status link_info; struct i40e_link_status link_info;
struct i40e_link_status link_info_old; struct i40e_link_status link_info_old;
bool get_link_info; bool get_link_info;
enum i40e_media_type media_type; enum i40e_media_type media_type;
/* all the phy types the NVM is capable of */ /* all the phy types the NVM is capable of */
enum i40e_aq_capabilities_phy_type phy_types; u32 phy_types;
}; };
#define I40E_HW_CAP_MAX_GPIO 30 #define I40E_HW_CAP_MAX_GPIO 30
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
/* Capabilities of a PF or a VF or the whole device */ /* Capabilities of a PF or a VF or the whole device */
struct i40e_hw_capabilities { struct i40e_hw_capabilities {
▲ Show 20 Lines • Show All 236 Lines • ▼ Show 20 Linesstruct i40e_dcb_app_priority_table {
u8 selector; u8 selector;
u16 protocolid; u16 protocolid;
}; };
struct i40e_dcbx_config { struct i40e_dcbx_config {
u8 dcbx_mode; u8 dcbx_mode;
#define I40E_DCBX_MODE_CEE 0x1 #define I40E_DCBX_MODE_CEE 0x1
#define I40E_DCBX_MODE_IEEE 0x2 #define I40E_DCBX_MODE_IEEE 0x2
u8 app_mode;
#define I40E_DCBX_APPS_NON_WILLING 0x1
u32 numapps; u32 numapps;
u32 tlv_status; /* CEE mode TLV status */ u32 tlv_status; /* CEE mode TLV status */
struct i40e_dcb_ets_config etscfg; struct i40e_dcb_ets_config etscfg;
struct i40e_dcb_ets_config etsrec; struct i40e_dcb_ets_config etsrec;
struct i40e_dcb_pfc_config pfc; struct i40e_dcb_pfc_config pfc;
struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
}; };
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesstruct i40e_hw {
/* LLDP/DCBX Status */ /* LLDP/DCBX Status */
u16 dcbx_status; u16 dcbx_status;
/* DCBX info */ /* DCBX info */
struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
u64 flags;
/* debug mask */ /* debug mask */
u32 debug_mask; u32 debug_mask;
char err_str[16]; char err_str[16];
}; };
static INLINE bool i40e_is_vf(struct i40e_hw *hw) static INLINE bool i40e_is_vf(struct i40e_hw *hw)
{ {
#ifdef X722_SUPPORT
return (hw->mac.type == I40E_MAC_VF ||
hw->mac.type == I40E_MAC_X722_VF);
#else
return hw->mac.type == I40E_MAC_VF; return hw->mac.type == I40E_MAC_VF;
#endif
} }
struct i40e_driver_version { struct i40e_driver_version {
u8 major_version; u8 major_version;
u8 minor_version; u8 minor_version;
u8 build_version; u8 build_version;
u8 subbuild_version; u8 subbuild_version;
u8 driver_string[32]; u8 driver_string[32];
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Linesenum i40e_rx_desc_status_bits {
/* Note: These are predefined bit offsets */ /* Note: These are predefined bit offsets */
I40E_RX_DESC_STATUS_DD_SHIFT = 0, I40E_RX_DESC_STATUS_DD_SHIFT = 0,
I40E_RX_DESC_STATUS_EOF_SHIFT = 1, I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
#ifdef X722_SUPPORT
I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
#else
I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8, I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
#endif
I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
I40E_RX_DESC_STATUS_FLM_SHIFT = 11, I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
#ifdef X722_SUPPORT
I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
#else
I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
#endif
I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
}; };
#define I40E_RXD_QW1_STATUS_SHIFT 0 #define I40E_RXD_QW1_STATUS_SHIFT 0
#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \ #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
I40E_RXD_QW1_STATUS_SHIFT) I40E_RXD_QW1_STATUS_SHIFT)
#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
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#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
I40E_TXD_CTX_QW0_NATLEN_SHIFT) I40E_TXD_CTX_QW0_NATLEN_SHIFT)
#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
I40E_TXD_CTX_QW0_DECTTL_SHIFT) I40E_TXD_CTX_QW0_DECTTL_SHIFT)
#ifdef X722_SUPPORT
#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
#endif
struct i40e_nop_desc { struct i40e_nop_desc {
__le64 rsvd; __le64 rsvd;
__le64 dtype_cmd; __le64 dtype_cmd;
}; };
#define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
#define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
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#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
/* Packet Classifier Types for filters */ /* Packet Classifier Types for filters */
enum i40e_filter_pctype { enum i40e_filter_pctype {
#ifdef X722_SUPPORT
/* Note: Values 0-28 are reserved for future use.
* Value 29, 30, 32 are not supported on XL710 and X710.
*/
I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
#else
/* Note: Values 0-30 are reserved for future use */ /* Note: Values 0-30 are reserved for future use */
#endif
I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
#ifdef X722_SUPPORT
I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
#else
/* Note: Value 32 is reserved for future use */ /* Note: Value 32 is reserved for future use */
#endif
I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
#ifdef X722_SUPPORT
/* Note: Values 37-38 are reserved for future use.
* Value 39, 40, 42 are not supported on XL710 and X710.
*/
I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
#else
/* Note: Values 37-40 are reserved for future use */ /* Note: Values 37-40 are reserved for future use */
#endif
I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
#ifdef X722_SUPPORT
I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
#endif
I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
/* Note: Value 47 is reserved for future use */ /* Note: Value 47 is reserved for future use */
I40E_FILTER_PCTYPE_FCOE_OX = 48, I40E_FILTER_PCTYPE_FCOE_OX = 48,
I40E_FILTER_PCTYPE_FCOE_RX = 49, I40E_FILTER_PCTYPE_FCOE_RX = 49,
I40E_FILTER_PCTYPE_FCOE_OTHER = 50, I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
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enum i40e_filter_program_desc_fd_status { enum i40e_filter_program_desc_fd_status {
I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
}; };
#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
#define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
I40E_TXD_FLTR_QW1_CMD_SHIFT) I40E_TXD_FLTR_QW1_CMD_SHIFT)
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#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
I40E_TXD_FLTR_QW1_CMD_SHIFT) I40E_TXD_FLTR_QW1_CMD_SHIFT)
#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
#ifdef X722_SUPPORT
#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
I40E_TXD_FLTR_QW1_CMD_SHIFT)
#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
#endif
#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
enum i40e_filter_type { enum i40e_filter_type {
I40E_FLOW_DIRECTOR_FLTR = 0, I40E_FLOW_DIRECTOR_FLTR = 0,
I40E_PE_QUAD_HASH_FLTR = 1, I40E_PE_QUAD_HASH_FLTR = 1,
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