Differential D7802 Diff 20113 sys/dev/ixl/i40e_adminq_cmd.h

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sys/dev/ixl/i40e_adminq_cmd.h

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/* This header file defines the i40e Admin Queue commands and is shared between		/* This header file defines the i40e Admin Queue commands and is shared between
* i40e Firmware and Software.		* i40e Firmware and Software.
*		*
* This file needs to comply with the Linux Kernel coding style.		* This file needs to comply with the Linux Kernel coding style.
*/		*/

#define I40E_FW_API_VERSION_MAJOR 0x0001		#define I40E_FW_API_VERSION_MAJOR 0x0001
#ifdef X722_SUPPORT		#define I40E_FW_API_VERSION_MINOR 0x0005
#define I40E_FW_API_VERSION_MINOR 0x0003
#else
#define I40E_FW_API_VERSION_MINOR 0x0004
#endif

struct i40e_aq_desc {		struct i40e_aq_desc {
__le16 flags;		__le16 flags;
__le16 opcode;		__le16 opcode;
__le16 datalen;		__le16 datalen;
__le16 retval;		__le16 retval;
__le32 cookie_high;		__le32 cookie_high;
__le32 cookie_low;		__le32 cookie_low;
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines	enum i40e_admin_queue_opc {
i40e_aqc_opc_clear_pxe_mode = 0x0110,		i40e_aqc_opc_clear_pxe_mode = 0x0110,

/* internal switch commands */		/* internal switch commands */
i40e_aqc_opc_get_switch_config = 0x0200,		i40e_aqc_opc_get_switch_config = 0x0200,
i40e_aqc_opc_add_statistics = 0x0201,		i40e_aqc_opc_add_statistics = 0x0201,
i40e_aqc_opc_remove_statistics = 0x0202,		i40e_aqc_opc_remove_statistics = 0x0202,
i40e_aqc_opc_set_port_parameters = 0x0203,		i40e_aqc_opc_set_port_parameters = 0x0203,
i40e_aqc_opc_get_switch_resource_alloc = 0x0204,		i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
		i40e_aqc_opc_set_switch_config = 0x0205,
		i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
		i40e_aqc_opc_rx_ctl_reg_write = 0x0207,

i40e_aqc_opc_add_vsi = 0x0210,		i40e_aqc_opc_add_vsi = 0x0210,
i40e_aqc_opc_update_vsi_parameters = 0x0211,		i40e_aqc_opc_update_vsi_parameters = 0x0211,
i40e_aqc_opc_get_vsi_parameters = 0x0212,		i40e_aqc_opc_get_vsi_parameters = 0x0212,

i40e_aqc_opc_add_pv = 0x0220,		i40e_aqc_opc_add_pv = 0x0220,
i40e_aqc_opc_update_pv_parameters = 0x0221,		i40e_aqc_opc_update_pv_parameters = 0x0221,
i40e_aqc_opc_get_pv_parameters = 0x0222,		i40e_aqc_opc_get_pv_parameters = 0x0222,
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines	enum i40e_admin_queue_opc {
i40e_aqc_opc_set_phy_int_mask = 0x0613,		i40e_aqc_opc_set_phy_int_mask = 0x0613,
i40e_aqc_opc_get_local_advt_reg = 0x0614,		i40e_aqc_opc_get_local_advt_reg = 0x0614,
i40e_aqc_opc_set_local_advt_reg = 0x0615,		i40e_aqc_opc_set_local_advt_reg = 0x0615,
i40e_aqc_opc_get_partner_advt = 0x0616,		i40e_aqc_opc_get_partner_advt = 0x0616,
i40e_aqc_opc_set_lb_modes = 0x0618,		i40e_aqc_opc_set_lb_modes = 0x0618,
i40e_aqc_opc_get_phy_wol_caps = 0x0621,		i40e_aqc_opc_get_phy_wol_caps = 0x0621,
i40e_aqc_opc_set_phy_debug = 0x0622,		i40e_aqc_opc_set_phy_debug = 0x0622,
i40e_aqc_opc_upload_ext_phy_fm = 0x0625,		i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
		i40e_aqc_opc_run_phy_activity = 0x0626,

/* NVM commands */		/* NVM commands */
i40e_aqc_opc_nvm_read = 0x0701,		i40e_aqc_opc_nvm_read = 0x0701,
i40e_aqc_opc_nvm_erase = 0x0702,		i40e_aqc_opc_nvm_erase = 0x0702,
i40e_aqc_opc_nvm_update = 0x0703,		i40e_aqc_opc_nvm_update = 0x0703,
i40e_aqc_opc_nvm_config_read = 0x0704,		i40e_aqc_opc_nvm_config_read = 0x0704,
i40e_aqc_opc_nvm_config_write = 0x0705,		i40e_aqc_opc_nvm_config_write = 0x0705,
i40e_aqc_opc_oem_post_update = 0x0720,		i40e_aqc_opc_oem_post_update = 0x0720,
		i40e_aqc_opc_thermal_sensor = 0x0721,

/* virtualization commands */		/* virtualization commands */
i40e_aqc_opc_send_msg_to_pf = 0x0801,		i40e_aqc_opc_send_msg_to_pf = 0x0801,
i40e_aqc_opc_send_msg_to_vf = 0x0802,		i40e_aqc_opc_send_msg_to_vf = 0x0802,
i40e_aqc_opc_send_msg_to_peer = 0x0803,		i40e_aqc_opc_send_msg_to_peer = 0x0803,

/* alternate structure */		/* alternate structure */
i40e_aqc_opc_alternate_write = 0x0900,		i40e_aqc_opc_alternate_write = 0x0900,
Show All 14 Lines	enum i40e_admin_queue_opc {
i40e_aqc_opc_lldp_start = 0x0A06,		i40e_aqc_opc_lldp_start = 0x0A06,
i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,		i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
i40e_aqc_opc_lldp_set_local_mib = 0x0A08,		i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,		i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,

/* Tunnel commands */		/* Tunnel commands */
i40e_aqc_opc_add_udp_tunnel = 0x0B00,		i40e_aqc_opc_add_udp_tunnel = 0x0B00,
i40e_aqc_opc_del_udp_tunnel = 0x0B01,		i40e_aqc_opc_del_udp_tunnel = 0x0B01,
#ifdef X722_SUPPORT
i40e_aqc_opc_set_rss_key = 0x0B02,
i40e_aqc_opc_set_rss_lut = 0x0B03,
i40e_aqc_opc_get_rss_key = 0x0B04,
i40e_aqc_opc_get_rss_lut = 0x0B05,
#endif

/* Async Events */		/* Async Events */
i40e_aqc_opc_event_lan_overflow = 0x1001,		i40e_aqc_opc_event_lan_overflow = 0x1001,

/* OEM commands */		/* OEM commands */
i40e_aqc_opc_oem_parameter_change = 0xFE00,		i40e_aqc_opc_oem_parameter_change = 0xFE00,
i40e_aqc_opc_oem_device_status_change = 0xFE01,		i40e_aqc_opc_oem_device_status_change = 0xFE01,
i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,		i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
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/* list of caps */		/* list of caps */

#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001		#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
#define I40E_AQ_CAP_ID_MNG_MODE 0x0002		#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003		#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004		#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005		#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006		#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
		#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
#define I40E_AQ_CAP_ID_SRIOV 0x0012		#define I40E_AQ_CAP_ID_SRIOV 0x0012
#define I40E_AQ_CAP_ID_VF 0x0013		#define I40E_AQ_CAP_ID_VF 0x0013
#define I40E_AQ_CAP_ID_VMDQ 0x0014		#define I40E_AQ_CAP_ID_VMDQ 0x0014
#define I40E_AQ_CAP_ID_8021QBG 0x0015		#define I40E_AQ_CAP_ID_8021QBG 0x0015
#define I40E_AQ_CAP_ID_8021QBR 0x0016		#define I40E_AQ_CAP_ID_8021QBR 0x0016
#define I40E_AQ_CAP_ID_VSI 0x0017		#define I40E_AQ_CAP_ID_VSI 0x0017
#define I40E_AQ_CAP_ID_DCB 0x0018		#define I40E_AQ_CAP_ID_DCB 0x0018
#define I40E_AQ_CAP_ID_FCOE 0x0021		#define I40E_AQ_CAP_ID_FCOE 0x0021
#define I40E_AQ_CAP_ID_ISCSI 0x0022		#define I40E_AQ_CAP_ID_ISCSI 0x0022
#define I40E_AQ_CAP_ID_RSS 0x0040		#define I40E_AQ_CAP_ID_RSS 0x0040
#define I40E_AQ_CAP_ID_RXQ 0x0041		#define I40E_AQ_CAP_ID_RXQ 0x0041
#define I40E_AQ_CAP_ID_TXQ 0x0042		#define I40E_AQ_CAP_ID_TXQ 0x0042
#define I40E_AQ_CAP_ID_MSIX 0x0043		#define I40E_AQ_CAP_ID_MSIX 0x0043
#define I40E_AQ_CAP_ID_VF_MSIX 0x0044		#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045		#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
#define I40E_AQ_CAP_ID_1588 0x0046		#define I40E_AQ_CAP_ID_1588 0x0046
#define I40E_AQ_CAP_ID_IWARP 0x0051		#define I40E_AQ_CAP_ID_IWARP 0x0051
#define I40E_AQ_CAP_ID_LED 0x0061		#define I40E_AQ_CAP_ID_LED 0x0061
#define I40E_AQ_CAP_ID_SDP 0x0062		#define I40E_AQ_CAP_ID_SDP 0x0062
#define I40E_AQ_CAP_ID_MDIO 0x0063		#define I40E_AQ_CAP_ID_MDIO 0x0063
		#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
#define I40E_AQ_CAP_ID_FLEX10 0x00F1		#define I40E_AQ_CAP_ID_FLEX10 0x00F1
#define I40E_AQ_CAP_ID_CEM 0x00F2		#define I40E_AQ_CAP_ID_CEM 0x00F2

/* Set CPPM Configuration (direct 0x0103) */		/* Set CPPM Configuration (direct 0x0103) */
struct i40e_aqc_cppm_configuration {		struct i40e_aqc_cppm_configuration {
__le16 command_flags;		__le16 command_flags;
#define I40E_AQ_CPPM_EN_LTRC 0x0800		#define I40E_AQ_CPPM_EN_LTRC 0x0800
#define I40E_AQ_CPPM_EN_DMCTH 0x1000		#define I40E_AQ_CPPM_EN_DMCTH 0x1000
▲ Show 20 Lines • Show All 242 Lines • ▼ Show 20 Lines	#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
__le16 total;		__le16 total;
__le16 used;		__le16 used;
__le16 total_unalloced;		__le16 total_unalloced;
u8 reserved2[6];		u8 reserved2[6];
};		};

I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);		I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);

		/* Set Switch Configuration (direct 0x0205) */
		struct i40e_aqc_set_switch_config {
		__le16 flags;
		#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
		#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
		__le16 valid_flags;
		u8 reserved[12];
		};

		I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);

		/* Read Receive control registers (direct 0x0206)
		* Write Receive control registers (direct 0x0207)
		* used for accessing Rx control registers that can be
		* slow and need special handling when under high Rx load
		*/
		struct i40e_aqc_rx_ctl_reg_read_write {
		__le32 reserved1;
		__le32 address;
		__le32 reserved2;
		__le32 value;
		};

		I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);

/* Add VSI (indirect 0x0210)		/* Add VSI (indirect 0x0210)
* this indirect command uses struct i40e_aqc_vsi_properties_data		* this indirect command uses struct i40e_aqc_vsi_properties_data
* as the indirect buffer (128 bytes)		* as the indirect buffer (128 bytes)
*		*
* Update VSI (indirect 0x211)		* Update VSI (indirect 0x211)
* uses the same data structure as Add VSI		* uses the same data structure as Add VSI
*		*
* Get VSI (indirect 0x0212)		* Get VSI (indirect 0x0212)
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#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0		#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \		#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)		I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9		#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \		#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)		I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
/* queueing option section */		/* queueing option section */
u8 queueing_opt_flags;		u8 queueing_opt_flags;
#ifdef X722_SUPPORT
#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
#endif
#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10		#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20		#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
#ifdef X722_SUPPORT
#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
#endif
u8 queueing_opt_reserved[3];		u8 queueing_opt_reserved[3];
/* scheduler section */		/* scheduler section */
u8 up_enable_bits;		u8 up_enable_bits;
u8 sched_reserved;		u8 sched_reserved;
/* outer up section */		/* outer up section */
__le32 outer_up_table; /* same structure and defines as ingress table */		__le32 outer_up_table; /* same structure and defines as ingress tbl */
u8 cmd_reserved[8];		u8 cmd_reserved[8];
/* last 32 bytes are written by FW */		/* last 32 bytes are written by FW */
__le16 qs_handle[8];		__le16 qs_handle[8];
#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF		#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
__le16 stat_counter_idx;		__le16 stat_counter_idx;
__le16 sched_id;		__le16 sched_id;
u8 resp_reserved[12];		u8 resp_reserved[12];
};		};
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines	struct i40e_aqc_add_veb {
__le16 downlink_seid;		__le16 downlink_seid;
__le16 veb_flags;		__le16 veb_flags;
#define I40E_AQC_ADD_VEB_FLOATING 0x1		#define I40E_AQC_ADD_VEB_FLOATING 0x1
#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1		#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \		#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)		I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2		#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4		#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8		#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
		#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
u8 enable_tcs;		u8 enable_tcs;
u8 reserved[9];		u8 reserved[9];
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);		I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);

struct i40e_aqc_add_veb_completion {		struct i40e_aqc_add_veb_completion {
u8 reserved[6];		u8 reserved[6];
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struct i40e_aqc_add_macvlan_element_data {		struct i40e_aqc_add_macvlan_element_data {
u8 mac_addr[6];		u8 mac_addr[6];
__le16 vlan_tag;		__le16 vlan_tag;
__le16 flags;		__le16 flags;
#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001		#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002		#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004		#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008		#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
		#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
__le16 queue_number;		__le16 queue_number;
#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0		#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \		#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)		I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
/* response section */		/* response section */
u8 match_method;		u8 match_method;
#define I40E_AQC_MM_PERFECT_MATCH 0x01		#define I40E_AQC_MM_PERFECT_MATCH 0x01
#define I40E_AQC_MM_HASH_MATCH 0x02		#define I40E_AQC_MM_HASH_MATCH 0x02
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines	struct i40e_aqc_set_vsi_promiscuous_modes {
__le16 promiscuous_flags;		__le16 promiscuous_flags;
__le16 valid_flags;		__le16 valid_flags;
/* flags used for both fields above */		/* flags used for both fields above */
#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01		#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02		#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04		#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
#define I40E_AQC_SET_VSI_DEFAULT 0x08		#define I40E_AQC_SET_VSI_DEFAULT 0x08
#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10		#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
		#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
__le16 seid;		__le16 seid;
#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF		#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
__le16 vlan_tag;		__le16 vlan_tag;
#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF		#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000		#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
u8 reserved[8];		u8 reserved[8];
};		};

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#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080		#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6		#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0		#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0		#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100		#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100

#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
		#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5

		#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
		#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
		#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000

__le32 tenant_id;		__le32 tenant_id;
u8 reserved[4];		u8 reserved[4];
__le16 queue_number;		__le16 queue_number;
#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0		#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \		#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)		I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
u8 reserved2[14];		u8 reserved2[14];
/* response section */		/* response section */
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines	struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
u8 reserved[15];		u8 reserved[15];
__le16 tc_bw_credit[8];		__le16 tc_bw_credit[8];

/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */		/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
__le16 tc_bw_max[2];		__le16 tc_bw_max[2];
u8 reserved1[28];		u8 reserved1[28];
};		};

I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);		I40E_CHECK_STRUCT_LEN(0x40,
		i40e_aqc_configure_switching_comp_ets_bw_limit_data);

/* Configure Switching Component Bandwidth Allocation per Tc		/* Configure Switching Component Bandwidth Allocation per Tc
* (indirect 0x0417)		* (indirect 0x0417)
*/		*/
struct i40e_aqc_configure_switching_comp_bw_config_data {		struct i40e_aqc_configure_switching_comp_bw_config_data {
u8 tc_valid_bits;		u8 tc_valid_bits;
u8 reserved[2];		u8 reserved[2];
u8 absolute_credits; /* bool */		u8 absolute_credits; /* bool */
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
#define I40E_AQ_LINK_TX_DRAINED 0x01		#define I40E_AQ_LINK_TX_DRAINED 0x01
#define I40E_AQ_LINK_TX_FLUSHED 0x03		#define I40E_AQ_LINK_TX_FLUSHED 0x03
#define I40E_AQ_LINK_FORCED_40G 0x10		#define I40E_AQ_LINK_FORCED_40G 0x10
u8 loopback; /* use defines from i40e_aqc_set_lb_mode */		u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
__le16 max_frame_size;		__le16 max_frame_size;
u8 config;		u8 config;
#define I40E_AQ_CONFIG_CRC_ENA 0x04		#define I40E_AQ_CONFIG_CRC_ENA 0x04
#define I40E_AQ_CONFIG_PACING_MASK 0x78		#define I40E_AQ_CONFIG_PACING_MASK 0x78
u8 reserved[5];		u8 external_power_ability;
		#define I40E_AQ_LINK_POWER_CLASS_1 0x00
		#define I40E_AQ_LINK_POWER_CLASS_2 0x01
		#define I40E_AQ_LINK_POWER_CLASS_3 0x02
		#define I40E_AQ_LINK_POWER_CLASS_4 0x03
		u8 reserved[4];
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);		I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);

/* Set event mask command (direct 0x613) */		/* Set event mask command (direct 0x613) */
struct i40e_aqc_set_phy_int_mask {		struct i40e_aqc_set_phy_int_mask {
u8 reserved[8];		u8 reserved[8];
__le16 event_mask;		__le16 event_mask;
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);		I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);

enum i40e_aq_phy_reg_type {		enum i40e_aq_phy_reg_type {
I40E_AQC_PHY_REG_INTERNAL = 0x1,		I40E_AQC_PHY_REG_INTERNAL = 0x1,
I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,		I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3		I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
};		};

		/* Run PHY Activity (0x0626) */
		struct i40e_aqc_run_phy_activity {
		__le16 activity_id;
		u8 flags;
		u8 reserved1;
		__le32 control;
		__le32 data;
		u8 reserved2[4];
		};

		I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);

/* NVM Read command (indirect 0x0701)		/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)		* NVM Erase commands (direct 0x0702)
* NVM Update commands (indirect 0x0703)		* NVM Update commands (indirect 0x0703)
*/		*/
struct i40e_aqc_nvm_update {		struct i40e_aqc_nvm_update {
u8 command_flags;		u8 command_flags;
#define I40E_AQ_NVM_LAST_CMD 0x01		#define I40E_AQ_NVM_LAST_CMD 0x01
#define I40E_AQ_NVM_FLASH_ONLY 0x80		#define I40E_AQ_NVM_FLASH_ONLY 0x80
u8 module_pointer;		u8 module_pointer;
__le16 length;		__le16 length;
__le32 offset;		__le32 offset;
__le32 addr_high;		__le32 addr_high;
__le32 addr_low;		__le32 addr_low;
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);		I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);

/* NVM Config Read (indirect 0x0704) */		/* NVM Config Read (indirect 0x0704) */
struct i40e_aqc_nvm_config_read {		struct i40e_aqc_nvm_config_read {
__le16 cmd_flags;		__le16 cmd_flags;
#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1		#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0		#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1		#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
__le16 element_count;		__le16 element_count;
__le16 element_id; /* Feature/field ID */		__le16 element_id; /* Feature/field ID */
__le16 element_id_msw; /* MSWord of field ID */		__le16 element_id_msw; /* MSWord of field ID */
__le32 address_high;		__le32 address_high;
__le32 address_low;		__le32 address_low;
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);		I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);

/* NVM Config Write (indirect 0x0705) */		/* NVM Config Write (indirect 0x0705) */
struct i40e_aqc_nvm_config_write {		struct i40e_aqc_nvm_config_write {
__le16 cmd_flags;		__le16 cmd_flags;
__le16 element_count;		__le16 element_count;
u8 reserved[4];		u8 reserved[4];
__le32 address_high;		__le32 address_high;
__le32 address_low;		__le32 address_low;
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);		I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);

/* Used for 0x0704 as well as for 0x0705 commands */		/* Used for 0x0704 as well as for 0x0705 commands */
#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1		#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)		#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
		(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
#define I40E_AQ_ANVM_FEATURE 0		#define I40E_AQ_ANVM_FEATURE 0
#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)		#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
struct i40e_aqc_nvm_config_data_feature {		struct i40e_aqc_nvm_config_data_feature {
__le16 feature_id;		__le16 feature_id;
#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01		#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08		#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10		#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
__le16 feature_options;		__le16 feature_options;
__le16 feature_selection;		__le16 feature_selection;
};		};

I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);		I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);

struct i40e_aqc_nvm_config_data_immediate_field {		struct i40e_aqc_nvm_config_data_immediate_field {
__le32 field_id;		__le32 field_id;
__le32 field_value;		__le32 field_value;
__le16 field_options;		__le16 field_options;
__le16 reserved;		__le16 reserved;
};		};

I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);		I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);

/* OEM Post Update (indirect 0x0720)		/* OEM Post Update (indirect 0x0720)
* no command data struct used		* no command data struct used
*/		*/
struct i40e_aqc_nvm_oem_post_update {		struct i40e_aqc_nvm_oem_post_update {
#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01		#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
u8 sel_data;		u8 sel_data;
u8 reserved[7];		u8 reserved[7];
};		};

I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);		I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);

struct i40e_aqc_nvm_oem_post_update_buffer {		struct i40e_aqc_nvm_oem_post_update_buffer {
u8 str_len;		u8 str_len;
u8 dev_addr;		u8 dev_addr;
__le16 eeprom_addr;		__le16 eeprom_addr;
u8 data[36];		u8 data[36];
};		};

I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);		I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);

		/* Thermal Sensor (indirect 0x0721)
		* read or set thermal sensor configs and values
		* takes a sensor and command specific data buffer, not detailed here
		*/
		struct i40e_aqc_thermal_sensor {
		u8 sensor_action;
		#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
		#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
		#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
		u8 reserved[7];
		__le32 addr_high;
		__le32 addr_low;
		};

		I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);

/* Send to PF command (indirect 0x0801) id is only used by PF		/* Send to PF command (indirect 0x0801) id is only used by PF
* Send to VF command (indirect 0x0802) id is only used by PF		* Send to VF command (indirect 0x0802) id is only used by PF
* Send to Peer PF command (indirect 0x0803)		* Send to Peer PF command (indirect 0x0803)
*/		*/
struct i40e_aqc_pf_vf_message {		struct i40e_aqc_pf_vf_message {
__le32 id;		__le32 id;
u8 reserved[4];		u8 reserved[4];
__le32 addr_high;		__le32 addr_high;
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines

I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);		I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);

/* Set Local LLDP MIB (indirect 0x0A08)		/* Set Local LLDP MIB (indirect 0x0A08)
* Used to replace the local MIB of a given LLDP agent. e.g. DCBx		* Used to replace the local MIB of a given LLDP agent. e.g. DCBx
*/		*/
struct i40e_aqc_lldp_set_local_mib {		struct i40e_aqc_lldp_set_local_mib {
#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0		#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)		#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
		SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
		#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
		#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
		#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
		SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
		#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
u8 type;		u8 type;
u8 reserved0;		u8 reserved0;
__le16 length;		__le16 length;
u8 reserved1[4];		u8 reserved1[4];
__le32 address_high;		__le32 address_high;
__le32 address_low;		__le32 address_low;
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);		I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);

		struct i40e_aqc_lldp_set_local_mib_resp {
		#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
		u8 status;
		u8 reserved[15];
		};

		I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);

/* Stop/Start LLDP Agent (direct 0x0A09)		/* Stop/Start LLDP Agent (direct 0x0A09)
* Used for stopping/starting specific LLDP agent. e.g. DCBx		* Used for stopping/starting specific LLDP agent. e.g. DCBx
*/		*/
struct i40e_aqc_lldp_stop_start_specific_agent {		struct i40e_aqc_lldp_stop_start_specific_agent {
#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0		#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)		#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
		(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
u8 command;		u8 command;
u8 reserved[15];		u8 reserved[15];
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);		I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);

/* Add Udp Tunnel command and completion (direct 0x0B00) */		/* Add Udp Tunnel command and completion (direct 0x0B00) */
struct i40e_aqc_add_udp_tunnel {		struct i40e_aqc_add_udp_tunnel {
__le16 udp_port;		__le16 udp_port;
u8 reserved0[3];		u8 reserved0[3];
u8 protocol_type;		u8 protocol_type;
#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00		#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
#define I40E_AQC_TUNNEL_TYPE_NGE 0x01		#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10		#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
		#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
u8 reserved1[10];		u8 reserved1[10];
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);		I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);

struct i40e_aqc_add_udp_tunnel_completion {		struct i40e_aqc_add_udp_tunnel_completion {
__le16 udp_port;		__le16 udp_port;
u8 filter_entry_index;		u8 filter_entry_index;
u8 multiple_pfs;		u8 multiple_pfs;
#define I40E_AQC_SINGLE_PF 0x0		#define I40E_AQC_SINGLE_PF 0x0
#define I40E_AQC_MULTIPLE_PFS 0x1		#define I40E_AQC_MULTIPLE_PFS 0x1
u8 total_filters;		u8 total_filters;
u8 reserved[11];		u8 reserved[11];
};		};

Show All 12 Lines	struct i40e_aqc_del_udp_tunnel_completion {
__le16 udp_port;		__le16 udp_port;
u8 index; /* 0 to 15 */		u8 index; /* 0 to 15 */
u8 multiple_pfs;		u8 multiple_pfs;
u8 total_filters_used;		u8 total_filters_used;
u8 reserved1[11];		u8 reserved1[11];
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);		I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
#ifdef X722_SUPPORT

struct i40e_aqc_get_set_rss_key {
#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
__le16 vsi_id;
u8 reserved[6];
__le32 addr_high;
__le32 addr_low;
};

I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);

struct i40e_aqc_get_set_rss_key_data {
u8 standard_rss_key[0x28];
u8 extended_hash_key[0xc];
};

I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);

struct i40e_aqc_get_set_rss_lut {
#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
__le16 vsi_id;
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)

#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
__le16 flags;
u8 reserved[4];
__le32 addr_high;
__le32 addr_low;
};

I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
#endif

/* tunnel key structure 0x0B10 */		/* tunnel key structure 0x0B10 */

struct i40e_aqc_tunnel_key_structure {		struct i40e_aqc_tunnel_key_structure {
u8 key1_off;		u8 key1_off;
u8 key2_off;		u8 key2_off;
u8 key1_len; /* 0 to 15 */		u8 key1_len; /* 0 to 15 */
u8 key2_len; /* 0 to 15 */		u8 key2_len; /* 0 to 15 */
u8 flags;		u8 flags;
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines	struct i40e_aqc_debug_modify_internals {
u8 cluster_id;		u8 cluster_id;
u8 cluster_specific_params[7];		u8 cluster_specific_params[7];
__le32 address_high;		__le32 address_high;
__le32 address_low;		__le32 address_low;
};		};

I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);		I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);

#endif		#endif /* _I40E_ADMINQ_CMD_H_ */