Differential D7697 Diff 19798 sys/dev/pci/pcib_private.h

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sys/dev/pci/pcib_private.h

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	#define WIN_MEM 0x2	#define WIN_MEM 0x2
	#define WIN_PMEM 0x4	#define WIN_PMEM 0x4

		/*
		* PCI-Bridge AER support
		*/
		/* AER Bits clear settings based on PCIE base spec. 1.1 */
		#define BCLR_PCIE_STATUS 0xf
		#define BCLR_AER_UNC_STATUS 0x1ff030
		#define BCLR_AER_C_STATUS 0x31c1
		#define BCLR_AER_RTSTATUS 127
		#define AER_REC_MAXLEN 255

		struct AER_error_data {
		int error_number; /* Nth of error starts from 1 */
		const char *dev_name;
		int unit; /* device pcib #unit number of source */
		int pcie_cap_status; /* Status register from PCI-E extended cap. */
		int unc_err_status; /* uncorrectable error status */
		int unc_err_seve; /* uncorrectable error severity */
		int c_err_status; /* correctable error status */
		int AER_ECRC; /* ECRC check status */
		int root_err_status; /* Root complex error status */
		int err_src_ID; /* uncorrectable error source ID */
		int c_err_src_ID; /* correctable error source ID */
		};

		struct AER_node {
		int index;
		struct AER_error_data *AER_error_data_container;
		STAILQ_ENTRY(AER_node) next;
		};

	struct pcib_window {	struct pcib_window {
	pci_addr_t base; /* base address */	pci_addr_t base; /* base address */
	pci_addr_t limit; /* topmost address */	pci_addr_t limit; /* topmost address */
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	uint16_t secstat; /* secondary bus status register */	uint16_t secstat; /* secondary bus status register */
	uint16_t bridgectl; /* bridge control register */	uint16_t bridgectl; /* bridge control register */
	uint8_t seclat; /* secondary bus latency timer */	uint8_t seclat; /* secondary bus latency timer */

		int sc_irq_rid; /* Interrupt handler*/
		struct resource *sc_irq_res;
		void *sc_irq_cookie;
	};	};

	#define PCIB_SUPPORTED_ARI_VER 1	#define PCIB_SUPPORTED_ARI_VER 1
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