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Show First 20 Lines • Show All 3,413 Lines • ▼ Show 20 Lines	tlb1_init()

tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;		tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
kernsize += (tsz > 0) ? tsize2size(tsz) : 0;		kernsize += (tsz > 0) ? tsize2size(tsz) : 0;

/* Setup TLB miss defaults */		/* Setup TLB miss defaults */
set_mas4_defaults();		set_mas4_defaults();
}		}

		void
		pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
		{
		int i;
		tlb_entry_t e;

		for (i = 0; i < TLB1_ENTRIES && size > 0; i ++) {
		tlb1_read_entry(&e, i);
		if (!(e.mas1 & MAS1_VALID))
		continue;
		/*
		* FIXME: this code does not work if VA region
		* spans multiple TLB entries. This does not cause
		* problems right now but shall be fixed in the future
		*/
		if (va >= e.virt && (va + size) <= (e.virt + e.size)) {
		size -= e.size;
		e.mas1 &= ~MAS1_VALID;
		tlb1_write_entry(&e, i);
		}
		}
		}

vm_offset_t		vm_offset_t
pmap_early_io_map(vm_paddr_t pa, vm_size_t size)		pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
{		{
vm_paddr_t pa_base;		vm_paddr_t pa_base;
vm_offset_t va, sz;		vm_offset_t va, sz;
int i;		int i;
tlb_entry_t e;		tlb_entry_t e;

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