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Differential D7606 Diff 19571 head/sys/powerpc/booke/pmap.c

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head/sys/powerpc/booke/pmap.c

Show First 20 Lines • Show All 3,160 Lines • ▼ Show 20 Linestlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
entry->mas1 = mfspr(SPR_MAS1); entry->mas1 = mfspr(SPR_MAS1);
entry->mas2 = mfspr(SPR_MAS2); entry->mas2 = mfspr(SPR_MAS2);
entry->mas3 = mfspr(SPR_MAS3); entry->mas3 = mfspr(SPR_MAS3);
switch ((mfpvr() >> 16) & 0xFFFF) { switch ((mfpvr() >> 16) & 0xFFFF) {
case FSL_E500v2: case FSL_E500v2:
case FSL_E500mc: case FSL_E500mc:
case FSL_E5500: case FSL_E5500:
case FSL_E6500:
entry->mas7 = mfspr(SPR_MAS7); entry->mas7 = mfspr(SPR_MAS7);
break; break;
default: default:
entry->mas7 = 0; entry->mas7 = 0;
break; break;
} }
entry->virt = entry->mas2 & MAS2_EPN_MASK; entry->virt = entry->mas2 & MAS2_EPN_MASK;
Show All 24 Linestlb1_write_entry(tlb_entry_t *e, unsigned int idx)
__asm __volatile("isync"); __asm __volatile("isync");
mtspr(SPR_MAS2, e->mas2); mtspr(SPR_MAS2, e->mas2);
__asm __volatile("isync"); __asm __volatile("isync");
mtspr(SPR_MAS3, e->mas3); mtspr(SPR_MAS3, e->mas3);
__asm __volatile("isync"); __asm __volatile("isync");
switch ((mfpvr() >> 16) & 0xFFFF) { switch ((mfpvr() >> 16) & 0xFFFF) {
case FSL_E500mc: case FSL_E500mc:
case FSL_E5500: case FSL_E5500:
case FSL_E6500:
mtspr(SPR_MAS8, 0); mtspr(SPR_MAS8, 0);
__asm __volatile("isync"); __asm __volatile("isync");
/* FALLTHROUGH */ /* FALLTHROUGH */
case FSL_E500v2: case FSL_E500v2:
mtspr(SPR_MAS7, e->mas7); mtspr(SPR_MAS7, e->mas7);
__asm __volatile("isync"); __asm __volatile("isync");
break; break;
default: default:
▲ Show 20 Lines • Show All 378 Lines • Show Last 20 Lines