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sys/dev/bhnd/cores/chipc/chipcreg.h
| Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines | |||||
| #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ | #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ | ||||
| #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ | #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ | ||||
| #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ | #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ | ||||
| #define CHIPC_GPIOTIMEROUTMASK 0x8C | #define CHIPC_GPIOTIMEROUTMASK 0x8C | ||||
| /* clock control block */ | /* clock control registers (non-PMU devices) */ | ||||
| #define CHIPC_CLKC_N 0x90 | #define CHIPC_CLKC_N 0x90 | ||||
| #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ | #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ | ||||
| #define CHIPC_CLKC_PCI 0x98 /* m1 */ | #define CHIPC_CLKC_PCI 0x98 /* m1 */ | ||||
| #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ | #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ | ||||
| #define CHIPC_CLKC_M3 0xA0 /* cpu */ | #define CHIPC_CLKC_M3 0xA0 /* cpu */ | ||||
| #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ | #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ | ||||
| #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ | #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ | ||||
| #define CHIPC_CAPABILITIES_EXT 0xAC | #define CHIPC_CAPABILITIES_EXT 0xAC | ||||
| /* pll delay (registers rev >= 4) */ | /* pll/slowclk clock control registers (rev >= 4) */ | ||||
| #define CHIPC_PLL_ON_DELAY 0xB0 | #define CHIPC_PLL_ON_DELAY 0xB0 /* rev >= 4 */ | ||||
| #define CHIPC_PLL_FREFSEL_DELAY 0xB4 | #define CHIPC_PLL_FREFSEL_DELAY 0xB4 /* rev >= 4 */ | ||||
| #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* revs 6-9 */ | #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */ | ||||
| /* "instaclock" registers */ | /* "instaclock" clock control registers */ | ||||
| #define CHIPC_SYS_CLK_CTL 0xC0 /* rev >= 10 */ | #define CHIPC_SYS_CLK_CTL 0xC0 /* "instaclock" (rev >= 10) */ | ||||
| #define CHIPC_SYS_CLKSTATESTRETCH 0xC4 /* rev >= 10 */ | #define CHIPC_SYS_CLK_ST_STRETCH 0xC4 /* state strech (?) rev >= 10 */ | ||||
| /* indirect backplane access (rev >= 10) */ | /* indirect backplane access (rev >= 10) */ | ||||
| #define CHIPC_BP_ADDRLOW 0xD0 | #define CHIPC_BP_ADDRLOW 0xD0 | ||||
| #define CHIPC_BP_ADDRHIGH 0xD4 | #define CHIPC_BP_ADDRHIGH 0xD4 | ||||
| #define CHIPC_BP_DATA 0xD8 | #define CHIPC_BP_DATA 0xD8 | ||||
| #define CHIPC_BP_INDACCESS 0xE0 | #define CHIPC_BP_INDACCESS 0xE0 | ||||
| /* SPI/I2C (rev >= 37) */ | /* SPI/I2C (rev >= 37) */ | ||||
| #define CHIPC_GSIO_CTRL 0xE4 | #define CHIPC_GSIO_CTRL 0xE4 | ||||
| #define CHIPC_GSIO_ADDR 0xE8 | #define CHIPC_GSIO_ADDR 0xE8 | ||||
| #define CHIPC_GSIO_DATA 0xEC | #define CHIPC_GSIO_DATA 0xEC | ||||
| /* More clock dividers (corerev >= 32) */ | /* More clock dividers (corerev >= 32) */ | ||||
| #define CHIPC_CLKDIV2 0xF0 | #define CHIPC_CLKDIV2 0xF0 | ||||
| #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address | #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address | ||||
| * on BCMA devices */ | * on BCMA devices */ | ||||
| /* ExtBus control registers (rev >= 3) */ | /* ExtBus control registers (rev >= 3) */ | ||||
| #define CHIPC_PCMCIA_CFG 0x100 | #define CHIPC_PCMCIA_CFG 0x100 | ||||
| #define CHIPC_PCMCIA_MEMWAIT 0x104 | #define CHIPC_PCMCIA_MEMWAIT 0x104 | ||||
| #define CHIPC_PCMCIA_ATTRWAIT 0x108 | #define CHIPC_PCMCIA_ATTRWAIT 0x108 | ||||
| #define CHIPC_PCMCIA_IOWAIT 0x10C | #define CHIPC_PCMCIA_IOWAIT 0x10C | ||||
| #define CHIPC_IDE_CFG 0x110 | #define CHIPC_IDE_CFG 0x110 | ||||
| #define CHIPC_IDE_MEMWAIT 0x114 | #define CHIPC_IDE_MEMWAIT 0x114 | ||||
| #define CHIPC_IDE_ATTRWAIT 0x118 | #define CHIPC_IDE_ATTRWAIT 0x118 | ||||
| Show All 36 Lines | |||||
| #define CHIPC_CLK_CTL_ST 0x1E0 | #define CHIPC_CLK_CTL_ST 0x1E0 | ||||
| #define CHIPC_SPROM_HWWAR 0x19 | #define CHIPC_SPROM_HWWAR 0x19 | ||||
| #define CHIPC_UART_BASE 0x300 | #define CHIPC_UART_BASE 0x300 | ||||
| #define CHIPC_UART_SIZE 0x100 | #define CHIPC_UART_SIZE 0x100 | ||||
| #define CHIPC_UART_MAX 3 /**< max UART blocks */ | #define CHIPC_UART_MAX 3 /**< max UART blocks */ | ||||
| #define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) | #define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) | ||||
| /* PMU registers (rev >= 20) */ | /* PMU register block (rev >= 20) */ | ||||
| #define CHIPC_PMU_BASE 0x600 | #define CHIPC_PMU_BASE 0x600 | ||||
| #define CHIPC_PMU_SIZE 0x70 | #define CHIPC_PMU_SIZE 0x70 | ||||
| #define CHIPC_PMU_CTRL 0x600 | |||||
| #define CHIPC_PMU_CAP 0x604 | |||||
| #define CHIPC_PMU_ST 0x608 | |||||
| #define CHIPC_PMU_RES_STATE 0x60c | |||||
| #define CHIPC_PMU_RES_PENDING 0x610 | |||||
| #define CHIPC_PMU_TIMER 0x614 | |||||
| #define CHIPC_PMU_MIN_RES_MASK 0x618 | |||||
| #define CHIPC_PMU_MAX_RES_MASK 0x61c | |||||
| #define CHIPC_PMU_RES_TABLE_SEL 0x620 | |||||
| #define CHIPC_PMU_RES_DEP_MASK 0x624 | |||||
| #define CHIPC_PMU_RES_UPDN_TIMER 0x628 | |||||
| #define CHIPC_PMU_RES_TIMER 0x62C | |||||
| #define CHIPC_PMU_CLKSTRETCH 0x630 | |||||
| #define CHIPC_PMU_WATCHDOG 0x634 | |||||
| #define CHIPC_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ | |||||
| #define CHIPC_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ | |||||
| #define CHIPC_PMU_RES_REQ_TIMER_SEL 0x640 | |||||
| #define CHIPC_PMU_RES_REQ_TIMER 0x644 | |||||
| #define CHIPC_PMU_RES_REQ_MASK 0x648 | |||||
| #define CHIPC_CHIPCTL_ADDR 0x650 | |||||
| #define CHIPC_CHIPCTL_DATA 0x654 | |||||
| #define CHIPC_PMU_REG_CONTROL_ADDR 0x658 | |||||
| #define CHIPC_PMU_REG_CONTROL_DATA 0x65C | |||||
| #define CHIPC_PMU_PLL_CONTROL_ADDR 0x660 | |||||
| #define CHIPC_PMU_PLL_CONTROL_DATA 0x664 | |||||
| #define CHIPC_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ | |||||
| #define CHIPC_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ | |||||
| #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ | #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ | ||||
| #define CHIPC_SPROM_OTP_SIZE 0x400 | #define CHIPC_SPROM_OTP_SIZE 0x400 | ||||
| /** chipid */ | /** chipid */ | ||||
| #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ | #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ | ||||
| #define CHIPC_ID_CHIP_SHIFT 0 | #define CHIPC_ID_CHIP_SHIFT 0 | ||||
| #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ | #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ | ||||
| #define CHIPC_ID_REV_SHIFT 16 | #define CHIPC_ID_REV_SHIFT 16 | ||||
| Show All 21 Lines | |||||
| #define CHIPC_CAP_FLASH_SHIFT 8 | #define CHIPC_CAP_FLASH_SHIFT 8 | ||||
| #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ | #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ | ||||
| #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ | #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ | ||||
| #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ | #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ | ||||
| #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ | #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ | ||||
| #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ | #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ | ||||
| #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ | #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ | ||||
| #define CHIPC_CAP_PLL_SHIFT 15 | #define CHIPC_CAP_PLL_SHIFT 15 | ||||
| #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ | #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power/clock control */ | ||||
| #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ | #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ | ||||
| #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ | #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ | ||||
| #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ | #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ | ||||
| #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ | #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ | ||||
| #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ | #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ | ||||
| #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ | #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ | ||||
| #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ | #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ | ||||
| #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ | #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ | ||||
| Show All 31 Lines | #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) | ||||
| * | * | ||||
| * it is unknown whether this is supported on | * it is unknown whether this is supported on | ||||
| * any CC revs >= 32 that also vend CHIPC_CAP_* | * any CC revs >= 32 that also vend CHIPC_CAP_* | ||||
| * constants for OTP/SPROM/NVRAM availability. | * constants for OTP/SPROM/NVRAM availability. | ||||
| */ | */ | ||||
| #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 | #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 | ||||
| /* PLL type */ | /* PLL type */ | ||||
| #define CHIPC_PLL_NONE 0x00000000 | #define CHIPC_PLL_NONE 0x00 | ||||
| #define CHIPC_PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ | #define CHIPC_PLL_TYPE1 0x10 /* 48MHz base, 3 dividers */ | ||||
| #define CHIPC_PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ | #define CHIPC_PLL_TYPE2 0x20 /* 48MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ | #define CHIPC_PLL_TYPE3 0x30 /* 25MHz, 2 dividers */ | ||||
| #define CHIPC_PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ | #define CHIPC_PLL_TYPE4 0x08 /* 48MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ | #define CHIPC_PLL_TYPE5 0x18 /* 25MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ | #define CHIPC_PLL_TYPE6 0x28 /* 100/200 or 120/240 only */ | ||||
| #define CHIPC_PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ | #define CHIPC_PLL_TYPE7 0x38 /* 25MHz, 4 dividers */ | ||||
| /* ILP clock */ | /* dynamic clock control defines */ | ||||
| #define CHIPC_ILP_CLOCK 32000 | #define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ | ||||
| #define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ | |||||
| #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ | |||||
| #define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */ | |||||
| #define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */ | |||||
| #define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */ | |||||
| /* ALP clock on pre-PMU chips */ | #define CHIPC_ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ | ||||
| #define CHIPC_ALP_CLOCK 20000000 | #define CHIPC_ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ | ||||
| /* HT clock */ | /* Power Control Defines */ | ||||
| #define CHIPC_HT_CLOCK 80000000 | #define CHIPC_PLL_DELAY 150 /* us pll on delay */ | ||||
| #define CHIPC_FREF_DELAY 200 /* us fref change delay */ | |||||
| #define CHIPC_MIN_SLOW_CLK 32 /* us Slow clock period */ | |||||
| #define CHIPC_XTAL_ON_DELAY 1000 /* us crystal power-on delay */ | |||||
| /* corecontrol */ | /* corecontrol */ | ||||
| #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ | #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ | ||||
| #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | ||||
| #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ | #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ | ||||
| /* chipcontrol */ | /* chipcontrol */ | ||||
| #define CHIPCTRL_4321A0_DEFAULT 0x3a4 | #define CHIPCTRL_4321A0_DEFAULT 0x3a4 | ||||
| ▲ Show 20 Lines • Show All 239 Lines • ▼ Show 20 Lines | |||||
| #define CHIPC_SRC_LOCK 0x00000008 | #define CHIPC_SRC_LOCK 0x00000008 | ||||
| #define CHIPC_SRC_SIZE_MASK 0x00000006 | #define CHIPC_SRC_SIZE_MASK 0x00000006 | ||||
| #define CHIPC_SRC_SIZE_1K 0x00000000 | #define CHIPC_SRC_SIZE_1K 0x00000000 | ||||
| #define CHIPC_SRC_SIZE_4K 0x00000002 | #define CHIPC_SRC_SIZE_4K 0x00000002 | ||||
| #define CHIPC_SRC_SIZE_16K 0x00000004 | #define CHIPC_SRC_SIZE_16K 0x00000004 | ||||
| #define CHIPC_SRC_SIZE_SHIFT 1 | #define CHIPC_SRC_SIZE_SHIFT 1 | ||||
| #define CHIPC_SRC_PRESENT 0x00000001 | #define CHIPC_SRC_PRESENT 0x00000001 | ||||
| /* Fields in pmucontrol */ | |||||
| #define CHIPC_PCTL_ILP_DIV_MASK 0xffff0000 | |||||
| #define CHIPC_PCTL_ILP_DIV_SHIFT 16 | |||||
| #define CHIPC_PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ | |||||
| #define CHIPC_PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ | |||||
| #define CHIPC_PCTL_HT_REQ_EN 0x00000100 | |||||
| #define CHIPC_PCTL_ALP_REQ_EN 0x00000080 | |||||
| #define CHIPC_PCTL_XTALFREQ_MASK 0x0000007c | |||||
| #define CHIPC_PCTL_XTALFREQ_SHIFT 2 | |||||
| #define CHIPC_PCTL_ILP_DIV_EN 0x00000002 | |||||
| #define CHIPC_PCTL_LPO_SEL 0x00000001 | |||||
| /* Fields in clkstretch */ | |||||
| #define CHIPC_CSTRETCH_HT 0xffff0000 | |||||
| #define CHIPC_CSTRETCH_ALP 0x0000ffff | |||||
| /* gpiotimerval */ | /* gpiotimerval */ | ||||
| #define CHIPC_GPIO_ONTIME_SHIFT 16 | #define CHIPC_GPIO_ONTIME_SHIFT 16 | ||||
| /* clockcontrol_n */ | /* clockcontrol_n */ | ||||
| #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ | #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ | ||||
| #define CHIPC_CN_N1_SHIFT 0 | |||||
| #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ | #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ | ||||
| #define CHIPC_CN_N2_SHIFT 8 | #define CHIPC_CN_N2_SHIFT 8 | ||||
| #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ | #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ | ||||
| #define CHIPC_CN_PLLC_SHIFT 16 | #define CHIPC_CN_PLLC_SHIFT 16 | ||||
| /* clockcontrol_sb/pci/uart */ | /* clockcontrol_sb/pci/uart */ | ||||
| #define CHIPC_M1_MASK 0x3f /* m1 control */ | #define CHIPC_M1_MASK 0x3f /* m1 control */ | ||||
| #define CHIPC_M1_SHIFT 0 | |||||
| #define CHIPC_M2_MASK 0x3f00 /* m2 control */ | #define CHIPC_M2_MASK 0x3f00 /* m2 control */ | ||||
| #define CHIPC_M2_SHIFT 8 | #define CHIPC_M2_SHIFT 8 | ||||
| #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ | #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ | ||||
| #define CHIPC_M3_SHIFT 16 | #define CHIPC_M3_SHIFT 16 | ||||
| #define CHIPC_MC_MASK 0x1f000000 /* mux control */ | #define CHIPC_MC_MASK 0x1f000000 /* mux control */ | ||||
| #define CHIPC_MC_SHIFT 24 | #define CHIPC_MC_SHIFT 24 | ||||
| /* N3M Clock control magic field values */ | /* N3M Clock control magic field values */ | ||||
| ▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines | |||||
| #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ | #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ | ||||
| /* Interrupt Enable Register (IER) bits */ | /* Interrupt Enable Register (IER) bits */ | ||||
| #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ | #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ | ||||
| #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ | #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ | ||||
| #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ | #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ | ||||
| #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ | #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ | ||||
| /* pmustatus */ | |||||
| #define CHIPC_PST_EXTLPOAVAIL 0x0100 | |||||
| #define CHIPC_PST_WDRESET 0x0080 | |||||
| #define CHIPC_PST_INTPEND 0x0040 | |||||
| #define CHIPC_PST_SBCLKST 0x0030 | |||||
| #define CHIPC_PST_SBCLKST_ILP 0x0010 | |||||
| #define CHIPC_PST_SBCLKST_ALP 0x0020 | |||||
| #define CHIPC_PST_SBCLKST_HT 0x0030 | |||||
| #define CHIPC_PST_ALPAVAIL 0x0008 | |||||
| #define CHIPC_PST_HTAVAIL 0x0004 | |||||
| #define CHIPC_PST_RESINIT 0x0003 | |||||
| /* pmucapabilities */ | |||||
| #define CHIPC_PCAP_REV_MASK 0x000000ff | |||||
| #define CHIPC_PCAP_RC_MASK 0x00001f00 | |||||
| #define CHIPC_PCAP_RC_SHIFT 8 | |||||
| #define CHIPC_PCAP_TC_MASK 0x0001e000 | |||||
| #define CHIPC_PCAP_TC_SHIFT 13 | |||||
| #define CHIPC_PCAP_PC_MASK 0x001e0000 | |||||
| #define CHIPC_PCAP_PC_SHIFT 17 | |||||
| #define CHIPC_PCAP_VC_MASK 0x01e00000 | |||||
| #define CHIPC_PCAP_VC_SHIFT 21 | |||||
| #define CHIPC_PCAP_CC_MASK 0x1e000000 | |||||
| #define CHIPC_PCAP_CC_SHIFT 25 | |||||
| #define CHIPC_PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ | |||||
| #define CHIPC_PCAP5_PC_SHIFT 17 | |||||
| #define CHIPC_PCAP5_VC_MASK 0x07c00000 | |||||
| #define CHIPC_PCAP5_VC_SHIFT 22 | |||||
| #define CHIPC_PCAP5_CC_MASK 0xf8000000 | |||||
| #define CHIPC_PCAP5_CC_SHIFT 27 | |||||
| /* PMU Resource Request Timer registers */ | |||||
| /* This is based on PmuRev0 */ | |||||
| #define CHIPC_PRRT_TIME_MASK 0x03ff | |||||
| #define CHIPC_PRRT_INTEN 0x0400 | |||||
| #define CHIPC_PRRT_REQ_ACTIVE 0x0800 | |||||
| #define CHIPC_PRRT_ALP_REQ 0x1000 | |||||
| #define CHIPC_PRRT_HT_REQ 0x2000 | |||||
| /* PMU resource bit position */ | |||||
| #define CHIPC_PMURES_BIT(bit) (1 << (bit)) | |||||
| /* PMU resource number limit */ | |||||
| #define CHIPC_PMURES_MAX_RESNUM 30 | |||||
| /* PMU chip control0 register */ | |||||
| #define CHIPC_PMU_CHIPCTL0 0 | |||||
| /* PMU chip control1 register */ | |||||
| #define CHIPC_PMU_CHIPCTL1 1 | |||||
| #define CHIPC_PMU_CC1_RXC_DLL_BYPASS 0x00010000 | |||||
| #define CHIPC_PMU_CC1_IF_TYPE_MASK 0x00000030 | |||||
| #define CHIPC_PMU_CC1_IF_TYPE_RMII 0x00000000 | |||||
| #define CHIPC_PMU_CC1_IF_TYPE_MII 0x00000010 | |||||
| #define CHIPC_PMU_CC1_IF_TYPE_RGMII 0x00000020 | |||||
| #define CHIPC_PMU_CC1_SW_TYPE_MASK 0x000000c0 | |||||
| #define CHIPC_PMU_CC1_SW_TYPE_EPHY 0x00000000 | |||||
| #define CHIPC_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 | |||||
| #define CHIPC_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 | |||||
| #define CHIPC_PMU_CC1_SW_TYPE_RGMII 0x000000c0 | |||||
| /* PMU corerev and chip specific PLL controls. | |||||
| * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number | |||||
| * to differentiate different PLLs controlled by the same PMU rev. | |||||
| */ | |||||
| /* pllcontrol registers */ | |||||
| /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ | |||||
| #define CHIPC_PMU0_PLL0_PLLCTL0 0 | |||||
| #define CHIPC_PMU0_PLL0_PC0_PDIV_MASK 1 | |||||
| #define CHIPC_PMU0_PLL0_PC0_PDIV_FREQ 25000 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE 8 | |||||
| /* PC0_DIV_ARM for PLLOUT_ARM */ | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 | |||||
| #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 | |||||
| /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ | |||||
| #define CHIPC_PMU0_PLL0_PLLCTL1 1 | |||||
| #define CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 | |||||
| #define CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 | |||||
| #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 | |||||
| #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 | |||||
| #define CHIPC_PMU0_PLL0_PC1_STOP_MOD 0x00000040 | |||||
| /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ | |||||
| #define CHIPC_PMU0_PLL0_PLLCTL2 2 | |||||
| #define CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK 0xf | |||||
| #define CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 | |||||
| /* pllcontrol registers */ | |||||
| /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ | |||||
| #define CHIPC_PMU1_PLL0_PLLCTL0 0 | |||||
| #define CHIPC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 | |||||
| #define CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 | |||||
| #define CHIPC_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 | |||||
| #define CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT 24 | |||||
| /* m<x>div */ | |||||
| #define CHIPC_PMU1_PLL0_PLLCTL1 1 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff | |||||
| #define CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT 0 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT 8 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT 16 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 | |||||
| #define CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT 24 | |||||
| #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 | |||||
| #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) | |||||
| #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) | |||||
| /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ | |||||
| #define CHIPC_PMU1_PLL0_PLLCTL2 2 | |||||
| #define CHIPC_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff | |||||
| #define CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT 0 | |||||
| #define CHIPC_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 | |||||
| #define CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT 8 | |||||
| #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 | |||||
| #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 | |||||
| #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 | |||||
| #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ | |||||
| #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 | |||||
| #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 | |||||
| /* ndiv_frac */ | |||||
| #define CHIPC_PMU1_PLL0_PLLCTL3 3 | |||||
| #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff | |||||
| #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 | |||||
| /* pll_ctrl */ | |||||
| #define CHIPC_PMU1_PLL0_PLLCTL4 4 | |||||
| /* pll_ctrl, vco_rng, clkdrive_ch<x> */ | |||||
| #define CHIPC_PMU1_PLL0_PLLCTL5 5 | |||||
| #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 | |||||
| #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 | |||||
| /* PMU rev 2 control words */ | |||||
| #define CHIPC_PMU2_PHY_PLL_PLLCTL 4 | |||||
| #define CHIPC_PMU2_SI_PLL_PLLCTL 10 | |||||
| /* PMU rev 2 */ | |||||
| /* pllcontrol registers */ | |||||
| /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ | |||||
| #define CHIPC_PMU2_PLL_PLLCTL0 0 | |||||
| #define CHIPC_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 | |||||
| #define CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT 20 | |||||
| #define CHIPC_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 | |||||
| #define CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT 24 | |||||
| /* m<x>div */ | |||||
| #define CHIPC_PMU2_PLL_PLLCTL1 1 | |||||
| #define CHIPC_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff | |||||
| #define CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT 0 | |||||
| #define CHIPC_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 | |||||
| #define CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT 8 | |||||
| #define CHIPC_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 | |||||
| #define CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT 16 | |||||
| #define CHIPC_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 | |||||
| #define CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT 24 | |||||
| /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ | |||||
| #define CHIPC_PMU2_PLL_PLLCTL2 2 | |||||
| #define CHIPC_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff | |||||
| #define CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT 0 | |||||
| #define CHIPC_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 | |||||
| #define CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT 8 | |||||
| #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 | |||||
| #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 | |||||
| #define CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 | |||||
| #define CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 | |||||
| /* ndiv_frac */ | |||||
| #define CHIPC_PMU2_PLL_PLLCTL3 3 | |||||
| #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff | |||||
| #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 | |||||
| /* pll_ctrl */ | |||||
| #define CHIPC_PMU2_PLL_PLLCTL4 4 | |||||
| /* pll_ctrl, vco_rng, clkdrive_ch<x> */ | |||||
| #define CHIPC_PMU2_PLL_PLLCTL5 5 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 | |||||
| #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 | |||||
| /* PMU rev 5 (& 6) */ | |||||
| #define CHIPC_PMU5_PLL_P1P2_OFF 0 | |||||
| #define CHIPC_PMU5_PLL_P1_MASK 0x0f000000 | |||||
| #define CHIPC_PMU5_PLL_P1_SHIFT 24 | |||||
| #define CHIPC_PMU5_PLL_P2_MASK 0x00f00000 | |||||
| #define CHIPC_PMU5_PLL_P2_SHIFT 20 | |||||
| #define CHIPC_PMU5_PLL_M14_OFF 1 | |||||
| #define CHIPC_PMU5_PLL_MDIV_MASK 0x000000ff | |||||
| #define CHIPC_PMU5_PLL_MDIV_WIDTH 8 | |||||
| #define CHIPC_PMU5_PLL_NM5_OFF 2 | |||||
| #define CHIPC_PMU5_PLL_NDIV_MASK 0xfff00000 | |||||
| #define CHIPC_PMU5_PLL_NDIV_SHIFT 20 | |||||
| #define CHIPC_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 | |||||
| #define CHIPC_PMU5_PLL_NDIV_MODE_SHIFT 17 | |||||
| #define CHIPC_PMU5_PLL_FMAB_OFF 3 | |||||
| #define CHIPC_PMU5_PLL_MRAT_MASK 0xf0000000 | |||||
| #define CHIPC_PMU5_PLL_MRAT_SHIFT 28 | |||||
| #define CHIPC_PMU5_PLL_ABRAT_MASK 0x08000000 | |||||
| #define CHIPC_PMU5_PLL_ABRAT_SHIFT 27 | |||||
| #define CHIPC_PMU5_PLL_FDIV_MASK 0x07ffffff | |||||
| #define CHIPC_PMU5_PLL_PLLCTL_OFF 4 | |||||
| #define CHIPC_PMU5_PLL_PCHI_OFF 5 | |||||
| #define CHIPC_PMU5_PLL_PCHI_MASK 0x0000003f | |||||
| /* pmu XtalFreqRatio */ | |||||
| #define CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF | |||||
| #define CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 | |||||
| #define CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 | |||||
| /* Divider allocation in 4716/47162/5356/5357 */ | |||||
| #define CHIPC_PMU5_MAINPLL_CPU 1 | |||||
| #define CHIPC_PMU5_MAINPLL_MEM 2 | |||||
| #define CHIPC_PMU5_MAINPLL_SI 3 | |||||
| #define CHIPC_PMU7_PLL_PLLCTL7 7 | |||||
| #define CHIPC_PMU7_PLL_PLLCTL8 8 | |||||
| #define CHIPC_PMU7_PLL_PLLCTL11 11 | |||||
| /* PLL usage in 4716/47162 */ | |||||
| #define CHIPC_PMU4716_MAINPLL_PLL0 12 | |||||
| /* PLL usage in 5356/5357 */ | |||||
| #define CHIPC_PMU5356_MAINPLL_PLL0 0 | |||||
| #define CHIPC_PMU5357_MAINPLL_PLL0 0 | |||||
| /* 4716/47162 resources */ | |||||
| #define CHIPC_RES4716_PROC_PLL_ON 0x00000040 | |||||
| #define CHIPC_RES4716_PROC_HT_AVAIL 0x00000080 | |||||
| /* 4716/4717/4718 Chip specific ChipControl register bits */ | |||||
| #define CHIPC_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ | |||||
| /* 5354 resources */ | |||||
| #define CHIPC_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ | |||||
| #define CHIPC_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ | |||||
| #define CHIPC_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ | |||||
| #define CHIPC_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ | |||||
| #define CHIPC_RES5354_ILP_REQUEST 4 /* 0x00010 */ | |||||
| #define CHIPC_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ | |||||
| #define CHIPC_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ | |||||
| #define CHIPC_RES5354_ROM_SWITCH 7 /* 0x00080 */ | |||||
| #define CHIPC_RES5354_PA_REF_LDO 8 /* 0x00100 */ | |||||
| #define CHIPC_RES5354_RADIO_LDO 9 /* 0x00200 */ | |||||
| #define CHIPC_RES5354_AFE_LDO 10 /* 0x00400 */ | |||||
| #define CHIPC_RES5354_PLL_LDO 11 /* 0x00800 */ | |||||
| #define CHIPC_RES5354_BG_FILTBYP 12 /* 0x01000 */ | |||||
| #define CHIPC_RES5354_TX_FILTBYP 13 /* 0x02000 */ | |||||
| #define CHIPC_RES5354_RX_FILTBYP 14 /* 0x04000 */ | |||||
| #define CHIPC_RES5354_XTAL_PU 15 /* 0x08000 */ | |||||
| #define CHIPC_RES5354_XTAL_EN 16 /* 0x10000 */ | |||||
| #define CHIPC_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ | |||||
| #define CHIPC_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ | |||||
| #define CHIPC_RES5354_BB_PLL_PU 19 /* 0x80000 */ | |||||
| /* 5357 Chip specific ChipControl register bits */ | |||||
| #define CHIPC_CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ | |||||
| #define CHIPC_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ | |||||
| /* 4328 resources */ | |||||
| #define CHIPC_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ | |||||
| #define CHIPC_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ | |||||
| #define CHIPC_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ | |||||
| #define CHIPC_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ | |||||
| #define CHIPC_RES4328_ILP_REQUEST 4 /* 0x00010 */ | |||||
| #define CHIPC_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ | |||||
| #define CHIPC_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ | |||||
| #define CHIPC_RES4328_ROM_SWITCH 7 /* 0x00080 */ | |||||
| #define CHIPC_RES4328_PA_REF_LDO 8 /* 0x00100 */ | |||||
| #define CHIPC_RES4328_RADIO_LDO 9 /* 0x00200 */ | |||||
| #define CHIPC_RES4328_AFE_LDO 10 /* 0x00400 */ | |||||
| #define CHIPC_RES4328_PLL_LDO 11 /* 0x00800 */ | |||||
| #define CHIPC_RES4328_BG_FILTBYP 12 /* 0x01000 */ | |||||
| #define CHIPC_RES4328_TX_FILTBYP 13 /* 0x02000 */ | |||||
| #define CHIPC_RES4328_RX_FILTBYP 14 /* 0x04000 */ | |||||
| #define CHIPC_RES4328_XTAL_PU 15 /* 0x08000 */ | |||||
| #define CHIPC_RES4328_XTAL_EN 16 /* 0x10000 */ | |||||
| #define CHIPC_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ | |||||
| #define CHIPC_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ | |||||
| #define CHIPC_RES4328_BB_PLL_PU 19 /* 0x80000 */ | |||||
| /* 4325 A0/A1 resources */ | |||||
| #define CHIPC_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ | |||||
| #define CHIPC_RES4325_CBUCK_BURST 1 /* 0x00000002 */ | |||||
| #define CHIPC_RES4325_CBUCK_PWM 2 /* 0x00000004 */ | |||||
| #define CHIPC_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ | |||||
| #define CHIPC_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ | |||||
| #define CHIPC_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ | |||||
| #define CHIPC_RES4325_ILP_REQUEST 6 /* 0x00000040 */ | |||||
| #define CHIPC_RES4325_ABUCK_BURST 7 /* 0x00000080 */ | |||||
| #define CHIPC_RES4325_ABUCK_PWM 8 /* 0x00000100 */ | |||||
| #define CHIPC_RES4325_LNLDO1_PU 9 /* 0x00000200 */ | |||||
| #define CHIPC_RES4325_OTP_PU 10 /* 0x00000400 */ | |||||
| #define CHIPC_RES4325_LNLDO3_PU 11 /* 0x00000800 */ | |||||
| #define CHIPC_RES4325_LNLDO4_PU 12 /* 0x00001000 */ | |||||
| #define CHIPC_RES4325_XTAL_PU 13 /* 0x00002000 */ | |||||
| #define CHIPC_RES4325_ALP_AVAIL 14 /* 0x00004000 */ | |||||
| #define CHIPC_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ | |||||
| #define CHIPC_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ | |||||
| #define CHIPC_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ | |||||
| #define CHIPC_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ | |||||
| #define CHIPC_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ | |||||
| #define CHIPC_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ | |||||
| #define CHIPC_RES4325_HT_AVAIL 21 /* 0x00200000 */ | |||||
| /* 4325 B0/C0 resources */ | |||||
| #define CHIPC_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ | |||||
| #define CHIPC_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ | |||||
| #define CHIPC_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ | |||||
| #define CHIPC_RES4325B0_CLDO_PU 4 /* 0x00000010 */ | |||||
| /* 4325 C1 resources */ | |||||
| #define CHIPC_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ | |||||
| /* 4325 chip-specific ChipStatus register bits */ | /* 4325 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | ||||
| #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | ||||
| #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 | #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 | ||||
| #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 | #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 | ||||
| #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 | #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 | ||||
| #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 | #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 | ||||
| #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 | #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 | ||||
| #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 | #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 | ||||
| #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ | #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ | ||||
| #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 | #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 | ||||
| #define CHIPC_RES4329_RESERVED0 0 /* 0x00000001 */ | |||||
| #define CHIPC_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ | |||||
| #define CHIPC_RES4329_CBUCK_BURST 2 /* 0x00000004 */ | |||||
| #define CHIPC_RES4329_CBUCK_PWM 3 /* 0x00000008 */ | |||||
| #define CHIPC_RES4329_CLDO_PU 4 /* 0x00000010 */ | |||||
| #define CHIPC_RES4329_PALDO_PU 5 /* 0x00000020 */ | |||||
| #define CHIPC_RES4329_ILP_REQUEST 6 /* 0x00000040 */ | |||||
| #define CHIPC_RES4329_RESERVED7 7 /* 0x00000080 */ | |||||
| #define CHIPC_RES4329_RESERVED8 8 /* 0x00000100 */ | |||||
| #define CHIPC_RES4329_LNLDO1_PU 9 /* 0x00000200 */ | |||||
| #define CHIPC_RES4329_OTP_PU 10 /* 0x00000400 */ | |||||
| #define CHIPC_RES4329_RESERVED11 11 /* 0x00000800 */ | |||||
| #define CHIPC_RES4329_LNLDO2_PU 12 /* 0x00001000 */ | |||||
| #define CHIPC_RES4329_XTAL_PU 13 /* 0x00002000 */ | |||||
| #define CHIPC_RES4329_ALP_AVAIL 14 /* 0x00004000 */ | |||||
| #define CHIPC_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ | |||||
| #define CHIPC_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ | |||||
| #define CHIPC_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ | |||||
| #define CHIPC_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ | |||||
| #define CHIPC_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ | |||||
| #define CHIPC_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ | |||||
| #define CHIPC_RES4329_HT_AVAIL 21 /* 0x00200000 */ | |||||
| /* 4329 chip-specific ChipStatus register bits */ | /* 4329 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | ||||
| #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | ||||
| #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 | #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 | ||||
| #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 | #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 | ||||
| /* 4312 chip-specific ChipStatus register bits */ | /* 4312 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | ||||
| #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | ||||
| /* 4312 resources (all PMU chips with little memory constraint) */ | |||||
| #define CHIPC_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ | |||||
| #define CHIPC_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ | |||||
| #define CHIPC_RES4312_PA_REF_LDO 2 /* 0x00000004 */ | |||||
| #define CHIPC_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ | |||||
| #define CHIPC_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ | |||||
| #define CHIPC_RES4312_RADIO_LDO 5 /* 0x00000020 */ | |||||
| #define CHIPC_RES4312_ILP_REQUEST 6 /* 0x00000040 */ | |||||
| #define CHIPC_RES4312_BG_FILTBYP 7 /* 0x00000080 */ | |||||
| #define CHIPC_RES4312_TX_FILTBYP 8 /* 0x00000100 */ | |||||
| #define CHIPC_RES4312_RX_FILTBYP 9 /* 0x00000200 */ | |||||
| #define CHIPC_RES4312_XTAL_PU 10 /* 0x00000400 */ | |||||
| #define CHIPC_RES4312_ALP_AVAIL 11 /* 0x00000800 */ | |||||
| #define CHIPC_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ | |||||
| #define CHIPC_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ | |||||
| #define CHIPC_RES4312_HT_AVAIL 14 /* 0x00004000 */ | |||||
| /* 4322 resources */ | |||||
| #define CHIPC_RES4322_RF_LDO 0 | |||||
| #define CHIPC_RES4322_ILP_REQUEST 1 | |||||
| #define CHIPC_RES4322_XTAL_PU 2 | |||||
| #define CHIPC_RES4322_ALP_AVAIL 3 | |||||
| #define CHIPC_RES4322_SI_PLL_ON 4 | |||||
| #define CHIPC_RES4322_HT_SI_AVAIL 5 | |||||
| #define CHIPC_RES4322_PHY_PLL_ON 6 | |||||
| #define CHIPC_RES4322_HT_PHY_AVAIL 7 | |||||
| #define CHIPC_RES4322_OTP_PU 8 | |||||
| /* 4322 chip-specific ChipStatus register bits */ | /* 4322 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 | #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 | ||||
| #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK | #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK | ||||
| #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT | #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT | ||||
| #define CHIPC_CST4322_PCI_OR_USB 0x00000100 | #define CHIPC_CST4322_PCI_OR_USB 0x00000100 | ||||
| #define CHIPC_CST4322_BOOT_MASK 0x00000600 | #define CHIPC_CST4322_BOOT_MASK 0x00000600 | ||||
| #define CHIPC_CST4322_BOOT_SHIFT 9 | #define CHIPC_CST4322_BOOT_SHIFT 9 | ||||
| #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ | #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ | ||||
| Show All 11 Lines | |||||
| #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ | #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ | ||||
| #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ | #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ | ||||
| #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ | #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ | ||||
| #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ | #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ | ||||
| #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 | #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 | ||||
| #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 | #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 | ||||
| #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 | #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 | ||||
| /* 43224 chip-specific ChipControl register bits */ | |||||
| #define CHIPC_CCTRL43224_GPIO_TOGGLE 0x8000 | |||||
| #define CHIPC_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ | |||||
| #define CHIPC_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ | |||||
| /* 43236 resources */ | |||||
| #define CHIPC_RES43236_REGULATOR 0 | |||||
| #define CHIPC_RES43236_ILP_REQUEST 1 | |||||
| #define CHIPC_RES43236_XTAL_PU 2 | |||||
| #define CHIPC_RES43236_ALP_AVAIL 3 | |||||
| #define CHIPC_RES43236_SI_PLL_ON 4 | |||||
| #define CHIPC_RES43236_HT_SI_AVAIL 5 | |||||
| /* 43236 chip-specific ChipControl register bits */ | |||||
| #define CHIPC_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ | |||||
| #define CHIPC_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ | |||||
| #define CHIPC_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ | |||||
| #define CHIPC_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ | |||||
| #define CHIPC_CCTRL43236_GSIO (1<<4) /* 0 disable */ | |||||
| /* 43236 Chip specific ChipStatus register bits */ | /* 43236 Chip specific ChipStatus register bits */ | ||||
| #define CHIPC_CST43236_SFLASH_MASK 0x00000040 | #define CHIPC_CST43236_SFLASH_MASK 0x00000040 | ||||
| #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 | #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 | ||||
| #define CHIPC_CST43236_OTP_SEL_SHIFT 7 | #define CHIPC_CST43236_OTP_SEL_SHIFT 7 | ||||
| #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ | #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ | ||||
| #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ | #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ | ||||
| #define CHIPC_CST43236_BOOT_MASK 0x00001800 | #define CHIPC_CST43236_BOOT_MASK 0x00001800 | ||||
| #define CHIPC_CST43236_BOOT_SHIFT 11 | #define CHIPC_CST43236_BOOT_SHIFT 11 | ||||
| #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ | #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ | ||||
| #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ | #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ | ||||
| #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ | #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ | ||||
| #define CHIPC_CST43236_BOOT_FROM_INVALID 3 | #define CHIPC_CST43236_BOOT_FROM_INVALID 3 | ||||
| /* 4331 resources */ | /* 43237 Chip specific ChipStatus register bits */ | ||||
| #define CHIPC_RES4331_REGULATOR 0 | #define CHIPC_CST43237_BP_CLK 0x00000200 /* 96/80Mbps */ | ||||
| #define CHIPC_RES4331_ILP_REQUEST 1 | |||||
| #define CHIPC_RES4331_XTAL_PU 2 | |||||
| #define CHIPC_RES4331_ALP_AVAIL 3 | |||||
| #define CHIPC_RES4331_SI_PLL_ON 4 | |||||
| #define CHIPC_RES4331_HT_SI_AVAIL 5 | |||||
| /* 4331 chip-specific ChipControl register bits */ | /* 4331 Chip specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ | |||||
| #define CHIPC_CST4331_SPROM_PRESENT 0x00000002 | |||||
| #define CHIPC_CST4331_OTP_PRESENT 0x00000004 | |||||
| #define CHIPC_CST4331_LDO_RF 0x00000008 | |||||
| #define CHIPC_CST4331_LDO_PAR 0x00000010 | |||||
| /* 4331 chip-specific CHIPCTRL register bits */ | |||||
| #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ | #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ | ||||
| #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ | #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ | ||||
| #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ | #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ | ||||
| #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ | #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ | ||||
| #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ | #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ | ||||
| #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ | #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ | ||||
| #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ | #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ | ||||
| #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ | #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ | ||||
| #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ | #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ | ||||
| #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ | #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ | ||||
| #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ | #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ | ||||
| #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ | #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ | ||||
| #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ | #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ | ||||
| #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ | #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ | ||||
| #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ | #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ | ||||
| /* 4331 Chip specific ChipStatus register bits */ | |||||
| #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ | |||||
| #define CHIPC_CST4331_SPROM_PRESENT 0x00000002 | |||||
| #define CHIPC_CST4331_OTP_PRESENT 0x00000004 | |||||
| #define CHIPC_CST4331_LDO_RF 0x00000008 | |||||
| #define CHIPC_CST4331_LDO_PAR 0x00000010 | |||||
| /* 4315 resources */ | |||||
| #define CHIPC_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ | |||||
| #define CHIPC_RES4315_CBUCK_BURST 2 /* 0x00000004 */ | |||||
| #define CHIPC_RES4315_CBUCK_PWM 3 /* 0x00000008 */ | |||||
| #define CHIPC_RES4315_CLDO_PU 4 /* 0x00000010 */ | |||||
| #define CHIPC_RES4315_PALDO_PU 5 /* 0x00000020 */ | |||||
| #define CHIPC_RES4315_ILP_REQUEST 6 /* 0x00000040 */ | |||||
| #define CHIPC_RES4315_LNLDO1_PU 9 /* 0x00000200 */ | |||||
| #define CHIPC_RES4315_OTP_PU 10 /* 0x00000400 */ | |||||
| #define CHIPC_RES4315_LNLDO2_PU 12 /* 0x00001000 */ | |||||
| #define CHIPC_RES4315_XTAL_PU 13 /* 0x00002000 */ | |||||
| #define CHIPC_RES4315_ALP_AVAIL 14 /* 0x00004000 */ | |||||
| #define CHIPC_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ | |||||
| #define CHIPC_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ | |||||
| #define CHIPC_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ | |||||
| #define CHIPC_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ | |||||
| #define CHIPC_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ | |||||
| #define CHIPC_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ | |||||
| #define CHIPC_RES4315_HT_AVAIL 21 /* 0x00200000 */ | |||||
| /* 4315 chip-specific ChipStatus register bits */ | /* 4315 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK | ||||
| #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT | ||||
| #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ | #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ | ||||
| #define CHIPC_CST4315_RCAL_VALID 0x00000008 | #define CHIPC_CST4315_RCAL_VALID 0x00000008 | ||||
| #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 | #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 | ||||
| #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 | #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 | ||||
| #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ | #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ | ||||
| #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 | #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 | ||||
| #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 | #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 | ||||
| #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 | #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 | ||||
| /* 4319 resources */ | |||||
| #define CHIPC_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ | |||||
| #define CHIPC_RES4319_CBUCK_BURST 2 /* 0x00000004 */ | |||||
| #define CHIPC_RES4319_CBUCK_PWM 3 /* 0x00000008 */ | |||||
| #define CHIPC_RES4319_CLDO_PU 4 /* 0x00000010 */ | |||||
| #define CHIPC_RES4319_PALDO_PU 5 /* 0x00000020 */ | |||||
| #define CHIPC_RES4319_ILP_REQUEST 6 /* 0x00000040 */ | |||||
| #define CHIPC_RES4319_LNLDO1_PU 9 /* 0x00000200 */ | |||||
| #define CHIPC_RES4319_OTP_PU 10 /* 0x00000400 */ | |||||
| #define CHIPC_RES4319_LNLDO2_PU 12 /* 0x00001000 */ | |||||
| #define CHIPC_RES4319_XTAL_PU 13 /* 0x00002000 */ | |||||
| #define CHIPC_RES4319_ALP_AVAIL 14 /* 0x00004000 */ | |||||
| #define CHIPC_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ | |||||
| #define CHIPC_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ | |||||
| #define CHIPC_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ | |||||
| #define CHIPC_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ | |||||
| #define CHIPC_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ | |||||
| #define CHIPC_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ | |||||
| #define CHIPC_RES4319_HT_AVAIL 21 /* 0x00200000 */ | |||||
| /* 4319 chip-specific ChipStatus register bits */ | /* 4319 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 | #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 | ||||
| #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 | #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 | ||||
| #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 | #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 | ||||
| #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ | #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ | ||||
| #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT | #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT | ||||
| #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ | #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ | ||||
| #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 | #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 | ||||
| #define CHIPC_CST4319_ILPDIV_EN 0x00000800 | #define CHIPC_CST4319_ILPDIV_EN 0x00000800 | ||||
| #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 | #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 | ||||
| #define CHIPC_CST4319_LPO_SEL 0x00002000 | #define CHIPC_CST4319_LPO_SEL 0x00002000 | ||||
| #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 | #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 | ||||
| #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ | #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ | ||||
| #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 | #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 | ||||
| #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 | #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 | ||||
| #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 | #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 | ||||
| #define CHIPC_CST4319_RCAL_VALID 0x01000000 | #define CHIPC_CST4319_RCAL_VALID 0x01000000 | ||||
| #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 | #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 | ||||
| #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 | #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 | ||||
| #define CHIPC_PMU1_PLL0_CHIPCTL0 0 | |||||
| #define CHIPC_PMU1_PLL0_CHIPCTL1 1 | |||||
| #define CHIPC_PMU1_PLL0_CHIPCTL2 2 | |||||
| #define CHIPC_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 | |||||
| #define CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT 19 | |||||
| #define CHIPC_CCTL_4319USB_48MHZ_PLL_SEL 1 | |||||
| #define CHIPC_CCTL_4319USB_24MHZ_PLL_SEL 2 | |||||
| /* PMU resources for 4336 */ | |||||
| #define CHIPC_RES4336_CBUCK_LPOM 0 | |||||
| #define CHIPC_RES4336_CBUCK_BURST 1 | |||||
| #define CHIPC_RES4336_CBUCK_LP_PWM 2 | |||||
| #define CHIPC_RES4336_CBUCK_PWM 3 | |||||
| #define CHIPC_RES4336_CLDO_PU 4 | |||||
| #define CHIPC_RES4336_DIS_INT_RESET_PD 5 | |||||
| #define CHIPC_RES4336_ILP_REQUEST 6 | |||||
| #define CHIPC_RES4336_LNLDO_PU 7 | |||||
| #define CHIPC_RES4336_LDO3P3_PU 8 | |||||
| #define CHIPC_RES4336_OTP_PU 9 | |||||
| #define CHIPC_RES4336_XTAL_PU 10 | |||||
| #define CHIPC_RES4336_ALP_AVAIL 11 | |||||
| #define CHIPC_RES4336_RADIO_PU 12 | |||||
| #define CHIPC_RES4336_BG_PU 13 | |||||
| #define CHIPC_RES4336_VREG1p4_PU_PU 14 | |||||
| #define CHIPC_RES4336_AFE_PWRSW_PU 15 | |||||
| #define CHIPC_RES4336_RX_PWRSW_PU 16 | |||||
| #define CHIPC_RES4336_TX_PWRSW_PU 17 | |||||
| #define CHIPC_RES4336_BB_PWRSW_PU 18 | |||||
| #define CHIPC_RES4336_SYNTH_PWRSW_PU 19 | |||||
| #define CHIPC_RES4336_MISC_PWRSW_PU 20 | |||||
| #define CHIPC_RES4336_LOGEN_PWRSW_PU 21 | |||||
| #define CHIPC_RES4336_BBPLL_PWRSW_PU 22 | |||||
| #define CHIPC_RES4336_MACPHY_CLKAVAIL 23 | |||||
| #define CHIPC_RES4336_HT_AVAIL 24 | |||||
| #define CHIPC_RES4336_RSVD 25 | |||||
| /* 4336 chip-specific ChipStatus register bits */ | /* 4336 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 | #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 | ||||
| #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 | #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 | ||||
| #define CHIPC_CST4336_OTP_PRESENT 0x00000004 | #define CHIPC_CST4336_OTP_PRESENT 0x00000004 | ||||
| #define CHIPC_CST4336_ARMREMAP_0 0x00000008 | #define CHIPC_CST4336_ARMREMAP_0 0x00000008 | ||||
| #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 | #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 | ||||
| #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 | #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 | ||||
| #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 | #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 | ||||
| #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 | #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 | ||||
| #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 | #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 | ||||
| #define CHIPC_CST4336_LPO_SEL_SHIFT 6 | #define CHIPC_CST4336_LPO_SEL_SHIFT 6 | ||||
| #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 | #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 | ||||
| #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 | #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 | ||||
| #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 | #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 | ||||
| #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 | #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 | ||||
| /* 4330 resources */ | |||||
| #define CHIPC_RES4330_CBUCK_LPOM 0 | |||||
| #define CHIPC_RES4330_CBUCK_BURST 1 | |||||
| #define CHIPC_RES4330_CBUCK_LP_PWM 2 | |||||
| #define CHIPC_RES4330_CBUCK_PWM 3 | |||||
| #define CHIPC_RES4330_CLDO_PU 4 | |||||
| #define CHIPC_RES4330_DIS_INT_RESET_PD 5 | |||||
| #define CHIPC_RES4330_ILP_REQUEST 6 | |||||
| #define CHIPC_RES4330_LNLDO_PU 7 | |||||
| #define CHIPC_RES4330_LDO3P3_PU 8 | |||||
| #define CHIPC_RES4330_OTP_PU 9 | |||||
| #define CHIPC_RES4330_XTAL_PU 10 | |||||
| #define CHIPC_RES4330_ALP_AVAIL 11 | |||||
| #define CHIPC_RES4330_RADIO_PU 12 | |||||
| #define CHIPC_RES4330_BG_PU 13 | |||||
| #define CHIPC_RES4330_VREG1p4_PU_PU 14 | |||||
| #define CHIPC_RES4330_AFE_PWRSW_PU 15 | |||||
| #define CHIPC_RES4330_RX_PWRSW_PU 16 | |||||
| #define CHIPC_RES4330_TX_PWRSW_PU 17 | |||||
| #define CHIPC_RES4330_BB_PWRSW_PU 18 | |||||
| #define CHIPC_RES4330_SYNTH_PWRSW_PU 19 | |||||
| #define CHIPC_RES4330_MISC_PWRSW_PU 20 | |||||
| #define CHIPC_RES4330_LOGEN_PWRSW_PU 21 | |||||
| #define CHIPC_RES4330_BBPLL_PWRSW_PU 22 | |||||
| #define CHIPC_RES4330_MACPHY_CLKAVAIL 23 | |||||
| #define CHIPC_RES4330_HT_AVAIL 24 | |||||
| #define CHIPC_RES4330_5gRX_PWRSW_PU 25 | |||||
| #define CHIPC_RES4330_5gTX_PWRSW_PU 26 | |||||
| #define CHIPC_RES4330_5g_LOGEN_PWRSW_PU 27 | |||||
| /* 4330 chip-specific ChipStatus register bits */ | /* 4330 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ | #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ | ||||
| #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ | #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ | ||||
| #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ | #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ | ||||
| #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ | #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ | ||||
| #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ | #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ | ||||
| #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ | #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ | ||||
| #define CHIPC_CST4330_OTP_PRESENT 0x00000010 | #define CHIPC_CST4330_OTP_PRESENT 0x00000010 | ||||
| #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 | #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 | ||||
| #define CHIPC_CST4330_ARMREMAP_0 0x00000040 | #define CHIPC_CST4330_ARMREMAP_0 0x00000040 | ||||
| #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ | #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ | ||||
| #define CHIPC_CST4330_ILPDIV_EN 0x00000100 | #define CHIPC_CST4330_ILPDIV_EN 0x00000100 | ||||
| #define CHIPC_CST4330_LPO_SEL 0x00000200 | #define CHIPC_CST4330_LPO_SEL 0x00000200 | ||||
| #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 | #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 | ||||
| #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 | #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 | ||||
| #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 | #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 | ||||
| #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 | #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 | ||||
| #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 | #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 | ||||
| #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 | #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 | ||||
| #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 | #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 | ||||
| #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 | #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 | ||||
| /* 4313 resources */ | |||||
| #define CHIPC_RES4313_BB_PU_RSRC 0 | |||||
| #define CHIPC_RES4313_ILP_REQ_RSRC 1 | |||||
| #define CHIPC_RES4313_XTAL_PU_RSRC 2 | |||||
| #define CHIPC_RES4313_ALP_AVAIL_RSRC 3 | |||||
| #define CHIPC_RES4313_RADIO_PU_RSRC 4 | |||||
| #define CHIPC_RES4313_BG_PU_RSRC 5 | |||||
| #define CHIPC_RES4313_VREG1P4_PU_RSRC 6 | |||||
| #define CHIPC_RES4313_AFE_PWRSW_RSRC 7 | |||||
| #define CHIPC_RES4313_RX_PWRSW_RSRC 8 | |||||
| #define CHIPC_RES4313_TX_PWRSW_RSRC 9 | |||||
| #define CHIPC_RES4313_BB_PWRSW_RSRC 10 | |||||
| #define CHIPC_RES4313_SYNTH_PWRSW_RSRC 11 | |||||
| #define CHIPC_RES4313_MISC_PWRSW_RSRC 12 | |||||
| #define CHIPC_RES4313_BB_PLL_PWRSW_RSRC 13 | |||||
| #define CHIPC_RES4313_HT_AVAIL_RSRC 14 | |||||
| #define CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC 15 | |||||
| /* 4313 chip-specific ChipStatus register bits */ | /* 4313 chip-specific ChipStatus register bits */ | ||||
| #define CHIPC_CST4313_SPROM_PRESENT 1 | #define CHIPC_CST4313_SPROM_PRESENT 1 | ||||
| #define CHIPC_CST4313_OTP_PRESENT 2 | #define CHIPC_CST4313_OTP_PRESENT 2 | ||||
| #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 | #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 | ||||
| #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 | #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 | ||||
| /* 4313 Chip specific ChipControl register bits */ | |||||
| #define CHIPC_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ | |||||
| /* 43228 resources */ | |||||
| #define CHIPC_RES43228_NOT_USED 0 | |||||
| #define CHIPC_RES43228_ILP_REQUEST 1 | |||||
| #define CHIPC_RES43228_XTAL_PU 2 | |||||
| #define CHIPC_RES43228_ALP_AVAIL 3 | |||||
| #define CHIPC_RES43228_PLL_EN 4 | |||||
| #define CHIPC_RES43228_HT_PHY_AVAIL 5 | |||||
| /* 43228 chipstatus reg bits */ | /* 43228 chipstatus reg bits */ | ||||
| #define CHIPC_CST43228_ILP_DIV_EN 0x1 | #define CHIPC_CST43228_ILP_DIV_EN 0x1 | ||||
| #define CHIPC_CST43228_OTP_PRESENT 0x2 | #define CHIPC_CST43228_OTP_PRESENT 0x2 | ||||
| #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 | #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 | ||||
| #define CHIPC_CST43228_SDIO_MODE 0x8 | #define CHIPC_CST43228_SDIO_MODE 0x8 | ||||
| #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 | #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 | ||||
| #define CHIPC_CST43228_SDIO_RESET 0x20 | #define CHIPC_CST43228_SDIO_RESET 0x20 | ||||
| /* | |||||
| * Maximum delay for the PMU state transition in us. | |||||
| * This is an upper bound intended for spinwaits etc. | |||||
| */ | |||||
| #define CHIPC_PMU_MAX_TRANSITION_DLY 15000 | |||||
| /* PMU resource up transition time in ILP cycles */ | |||||
| #define CHIPC_PMURES_UP_TRANSITION 2 | |||||
| /* | /* | ||||
| * Register eci_inputlo bitfield values. | * Register eci_inputlo bitfield values. | ||||
| * - BT packet type information bits [7:0] | * - BT packet type information bits [7:0] | ||||
| */ | */ | ||||
| /* [3:0] - Task (link) type */ | /* [3:0] - Task (link) type */ | ||||
| #define CHIPC_BT_ACL 0x00 | #define CHIPC_BT_ACL 0x00 | ||||
| #define CHIPC_BT_SCO 0x01 | #define CHIPC_BT_SCO 0x01 | ||||
| Show All 23 Lines | |||||