Differential D7492 Diff 19372 sys/dev/bhnd/cores/chipc/chipc.c

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sys/dev/bhnd/cores/chipc/chipc.c

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines	static struct bhnd_device_quirk chipc_quirks[] = {
BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),		BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),

BHND_DEVICE_QUIRK_END		BHND_DEVICE_QUIRK_END
};		};

// FIXME: IRQ shouldn't be hard-coded		// FIXME: IRQ shouldn't be hard-coded
#define CHIPC_MIPS_IRQ 2		#define CHIPC_MIPS_IRQ 2

static int chipc_add_children(struct chipc_softc *sc);		static int chipc_add_children(struct chipc_softc *sc);

static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,		static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
struct chipc_caps *caps);		struct chipc_caps *caps);
static int chipc_read_caps(struct chipc_softc *sc,		static int chipc_read_caps(struct chipc_softc *sc,
struct chipc_caps *caps);		struct chipc_caps *caps);

static bool chipc_should_enable_sprom(		static bool chipc_should_enable_muxed_sprom(
struct chipc_softc *sc);		struct chipc_softc *sc);
		static int chipc_enable_otp_power(struct chipc_softc *sc);
		static void chipc_disable_otp_power(struct chipc_softc *sc);
		static int chipc_enable_sprom_pins(struct chipc_softc *sc);
		static void chipc_disable_sprom_pins(struct chipc_softc *sc);

static int chipc_try_activate_resource(		static int chipc_try_activate_resource(struct chipc_softc *sc,
struct chipc_softc *sc, device_t child,		device_t child, int type, int rid,
int type, int rid, struct resource *r,		struct resource *r, bool req_direct);
bool req_direct);

static int chipc_init_rman(struct chipc_softc *sc);		static int chipc_init_rman(struct chipc_softc *sc);
static void chipc_free_rman(struct chipc_softc *sc);		static void chipc_free_rman(struct chipc_softc *sc);
static struct rman chipc_get_rman(struct chipc_softc sc,		static struct rman chipc_get_rman(struct chipc_softc sc, int type);
int type);

/* quirk and capability flag convenience macros */		/* quirk and capability flag convenience macros */
#define CHIPC_QUIRK(_sc, _name) \		#define CHIPC_QUIRK(_sc, _name) \
((_sc)->quirks & CHIPC_QUIRK_ ## _name)		((_sc)->quirks & CHIPC_QUIRK_ ## _name)

#define CHIPC_CAP(_sc, _name) \		#define CHIPC_CAP(_sc, _name) \
((_sc)->caps._name)		((_sc)->caps._name)

▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines	if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM \|\|

/* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */		/* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,		error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0);		CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0);
if (error)		if (error)
return (error);		return (error);
}		}

#ifdef notyet
/*		/*
* PMU/SLOWCLK/INSTACLK		* PMU/PWR_CTRL
*		*
* On AOB ("Always on Bus") devices, a PMU core (if it exists) is		* On AOB ("Always on Bus") devices, the PMU core (if it exists) is
* enumerated directly by the bhnd(4) bus -- not chipc.		* attached directly to the bhnd(4) bus -- not chipc.
*
* Otherwise, we always add a PMU child device, and let the
* chipc bhnd_pmu drivers probe for it. If the core supports an
* earlier non-PMU clock/power register interface, one of the instaclk,
* powerctl, or null bhnd_pmu drivers will claim the device.
*/		*/
if (!sc->caps.aob \|\| (sc->caps.aob && !sc->caps.pmu)) {		if (sc->caps.pwr_ctrl \|\| (sc->caps.pmu && !sc->caps.aob)) {
child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);		child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
if (child == NULL) {		if (child == NULL) {
device_printf(sc->dev, "failed to add pmu\n");		device_printf(sc->dev, "failed to add pmu\n");
return (ENXIO);		return (ENXIO);
}		}

/* Associate the applicable register block */
error = 0;
if (sc->caps.pmu) {
error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
CHIPC_PMU, CHIPC_PMU_SIZE, 0, 0);
} else if (sc->caps.power_control) {
error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
CHIPC_PWRCTL, CHIPC_PWRCTL_SIZE, 0, 0);
}		}

if (error)
return (error);

}
#endif /* notyet */

/* All remaining devices are SoC-only */		/* All remaining devices are SoC-only */
if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)		if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
return (0);		return (0);

/* UARTs */		/* UARTs */
for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {		for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);		child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
if (child == NULL) {		if (child == NULL) {
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines	chipc_read_caps(struct chipc_softc sc, struct chipc_caps caps)

/* Extract values */		/* Extract values */
caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);		caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);		caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);		caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);		caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);

caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);		caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);		caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);		caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);

caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);		caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);		caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);		caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);		caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);		caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);		caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
▲ Show 20 Lines • Show All 650 Lines • ▼ Show 20 Lines
* Examine bus state and make a best effort determination of whether it's		* Examine bus state and make a best effort determination of whether it's
* likely safe to enable the muxed SPROM pins.		* likely safe to enable the muxed SPROM pins.
*		*
* On devices that do not use SPROM pin muxing, always returns true.		* On devices that do not use SPROM pin muxing, always returns true.
*		*
* @param sc chipc driver state.		* @param sc chipc driver state.
*/		*/
static bool		static bool
chipc_should_enable_sprom(struct chipc_softc *sc)		chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
{		{
device_t *devs;		device_t *devs;
device_t hostb;		device_t hostb;
device_t parent;		device_t parent;
int devcount;		int devcount;
int error;		int error;
bool result;		bool result;

mtx_assert(&Giant, MA_OWNED); /* for newbus */

/* Nothing to do? */		/* Nothing to do? */
if (!CHIPC_QUIRK(sc, MUX_SPROM))		if (!CHIPC_QUIRK(sc, MUX_SPROM))
return (true);		return (true);

		mtx_lock(&Giant); /* for newbus */

parent = device_get_parent(sc->dev);		parent = device_get_parent(sc->dev);
hostb = bhnd_find_hostb_device(parent);		hostb = bhnd_find_hostb_device(parent);

if ((error = device_get_children(parent, &devs, &devcount)))		if ((error = device_get_children(parent, &devs, &devcount))) {
		mtx_unlock(&Giant);
return (false);		return (false);
		}

/* Reject any active devices other than ChipCommon, or the		/* Reject any active devices other than ChipCommon, or the
* host bridge (if any). */		* host bridge (if any). */
result = true;		result = true;
for (int i = 0; i < devcount; i++) {		for (int i = 0; i < devcount; i++) {
if (devs[i] == hostb \|\| devs[i] == sc->dev)		if (devs[i] == hostb \|\| devs[i] == sc->dev)
continue;		continue;

if (!device_is_attached(devs[i]))		if (!device_is_attached(devs[i]))
continue;		continue;

if (device_is_suspended(devs[i]))		if (device_is_suspended(devs[i]))
continue;		continue;

/* Active device; assume SPROM is busy */		/* Active device; assume SPROM is busy */
result = false;		result = false;
break;		break;
}		}

free(devs, M_TEMP);		free(devs, M_TEMP);
		mtx_unlock(&Giant);
return (result);		return (result);
}		}

		static int
		chipc_enable_sprom(device_t dev)
		{
		struct chipc_softc *sc;
		int error;

		sc = device_get_softc(dev);
		CHIPC_LOCK(sc);

		/* Already enabled? */
		if (sc->sprom_refcnt >= 1) {
		sc->sprom_refcnt++;
		CHIPC_UNLOCK(sc);

		return (0);
		}

		switch (sc->caps.nvram_src) {
		case BHND_NVRAM_SRC_SPROM:
		error = chipc_enable_sprom_pins(sc);
		break;
		case BHND_NVRAM_SRC_OTP:
		error = chipc_enable_otp_power(sc);
		break;
		default:
		error = 0;
		break;
		}

		/* Bump the reference count */
		if (error == 0)
		sc->sprom_refcnt++;

		CHIPC_UNLOCK(sc);
		return (error);
		}

		static void
		chipc_disable_sprom(device_t dev)
		{
		struct chipc_softc *sc;

		sc = device_get_softc(dev);
		CHIPC_LOCK(sc);

		/* Check reference count, skip disable if in-use. */
		KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
		sc->sprom_refcnt--;
		if (sc->sprom_refcnt > 0) {
		CHIPC_UNLOCK(sc);
		return;
		}

		switch (sc->caps.nvram_src) {
		case BHND_NVRAM_SRC_SPROM:
		chipc_disable_sprom_pins(sc);
		break;
		case BHND_NVRAM_SRC_OTP:
		chipc_disable_otp_power(sc);
		break;
		default:
		break;
		}


		CHIPC_UNLOCK(sc);
		}

		static int
		chipc_enable_otp_power(struct chipc_softc *sc)
		{
		// TODO: Enable OTP resource via PMU, and wait up to 100 usec for
		// OTPS_READY to be set in `optstatus`.
		return (0);
		}

		static void
		chipc_disable_otp_power(struct chipc_softc *sc)
		{
		// TODO: Disable OTP resource via PMU
		}

/**		/**
* If required by this device, enable access to the SPROM.		* If required by this device, enable access to the SPROM.
*		*
* @param sc chipc driver state.		* @param sc chipc driver state.
*/		*/
static int		static int
chipc_enable_sprom_pins(device_t dev)		chipc_enable_sprom_pins(struct chipc_softc *sc)
{		{
struct chipc_softc *sc;
uint32_t cctrl;		uint32_t cctrl;
int error;

sc = device_get_softc(dev);		CHIPC_LOCK_ASSERT(sc, MA_OWNED);
		KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));

/* Nothing to do? */		/* Nothing to do? */
if (!CHIPC_QUIRK(sc, MUX_SPROM))		if (!CHIPC_QUIRK(sc, MUX_SPROM))
return (0);		return (0);

/* Make sure we're holding Giant for newbus */
mtx_lock(&Giant);
CHIPC_LOCK(sc);

/* Already enabled? */
if (sc->sprom_refcnt >= 1) {
error = 0;
goto finished;
}

/* Check whether bus is busy */		/* Check whether bus is busy */
if (!chipc_should_enable_sprom(sc)) {		if (!chipc_should_enable_muxed_sprom(sc))
error = EBUSY;		return (EBUSY);
goto finished;
}

cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);		cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);

/* 4331 devices */		/* 4331 devices */
if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {		if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;		cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;

if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))		if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;		cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;

if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))		if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;		cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;

bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);		bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
error = 0;		return (0);
goto finished;
}		}

/* 4360 devices */		/* 4360 devices */
if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {		if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
/* Unimplemented */		/* Unimplemented */
}		}

/* Refuse to proceed on unsupported devices with muxed SPROM pins */		/* Refuse to proceed on unsupported devices with muxed SPROM pins */
device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");		device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
error = ENXIO;		return (ENXIO);

finished:
/* Bump the reference count */
if (error == 0)
sc->sprom_refcnt++;

CHIPC_UNLOCK(sc);
mtx_unlock(&Giant);

return (error);
}		}

/**		/**
* If required by this device, revert any GPIO/pin configuration applied		* If required by this device, revert any GPIO/pin configuration applied
* to allow SPROM access.		* to allow SPROM access.
*		*
* @param sc chipc driver state.		* @param sc chipc driver state.
*/		*/
static void		static void
chipc_disable_sprom_pins(device_t dev)		chipc_disable_sprom_pins(struct chipc_softc *sc)
{		{
struct chipc_softc *sc;
uint32_t cctrl;		uint32_t cctrl;

sc = device_get_softc(dev);

/* Nothing to do? */		/* Nothing to do? */
if (!CHIPC_QUIRK(sc, MUX_SPROM))		if (!CHIPC_QUIRK(sc, MUX_SPROM))
return;		return;

CHIPC_LOCK(sc);		CHIPC_LOCK_ASSERT(sc, MA_OWNED);
		KASSERT(sc->sprom_refcnt != 0, ("sprom pins already disabled"));
		KASSERT(sc->sprom_refcnt == 1, ("sprom pins in use"));

/* Check reference count, skip disable if in-use. */
KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
sc->sprom_refcnt--;
if (sc->sprom_refcnt > 0)
goto finished;

cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);		cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);

/* 4331 devices */		/* 4331 devices */
if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {		if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
cctrl \|= CHIPC_CCTRL4331_EXTPA_EN;		cctrl \|= CHIPC_CCTRL4331_EXTPA_EN;

if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))		if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
cctrl \|= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;		cctrl \|= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;

if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))		if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
cctrl \|= CHIPC_CCTRL4331_EXTPA_EN2;		cctrl \|= CHIPC_CCTRL4331_EXTPA_EN2;

bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);		bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
goto finished;		return;
}		}

/* 4360 devices */		/* 4360 devices */
if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {		if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
/* Unimplemented */		/* Unimplemented */
}		}
		}

finished:		static uint32_t
CHIPC_UNLOCK(sc);		chipc_read_chipst(device_t dev)
		{
		struct chipc_softc *sc = device_get_softc(dev);
		return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
}		}

static void		static void
chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)		chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
{		{
struct chipc_softc *sc;		struct chipc_softc *sc;
uint32_t cctrl;		uint32_t cctrl;

▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	static device_method_t chipc_methods[] = {
DEVMETHOD(bus_config_intr, bus_generic_config_intr),		DEVMETHOD(bus_config_intr, bus_generic_config_intr),
DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),		DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),		DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),

/* BHND bus inteface */		/* BHND bus inteface */
DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),		DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),

/* ChipCommon interface */		/* ChipCommon interface */
		DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),		DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins),		DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins),		DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),		DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),

DEVMETHOD_END		DEVMETHOD_END
};		};

DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc));		DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0,		EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);		BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);		MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
MODULE_VERSION(bhnd_chipc, 1);		MODULE_VERSION(bhnd_chipc, 1);