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Differential D7493 Diff 19251 sys/arm/nvidia/tegra_lic.c

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sys/arm/nvidia/tegra_lic.c

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struct tegra_lic_sc { struct tegra_lic_sc {
device_t dev; device_t dev;
struct resource *mem_res[nitems(lic_spec)]; struct resource *mem_res[nitems(lic_spec)];
device_t parent; device_t parent;
}; };
static int static int
tegra_lic_alloc_intr(device_t dev, struct intr_irqsrc *isrc, tegra_lic_activate_intr(device_t dev, struct intr_irqsrc *isrc,
struct resource *res, struct intr_map_data *data) struct resource *res, struct intr_map_data *data)
{ {
struct tegra_lic_sc *sc = device_get_softc(dev); struct tegra_lic_sc *sc = device_get_softc(dev);
return (PIC_ALLOC_INTR(sc->parent, isrc, res, data)); return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
nwhitehornUnsubmitted
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As a general comment, I don't think these routines are necessary. Cascaded interrupt domains don't have to know about each other for any reason (and, on PowerPC, in fact do not). Note that this is not an issue for this patch, but is something that should be thought about longer-term.

nwhitehorn: As a general comment, I don't think these routines are necessary. Cascaded interrupt domains…
mmelAuthorUnsubmitted
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Tegra LIC is something special. It's not a cascaded (aka N: 1) but 'pass-through' (N:N) interrupt controller. Under normal circumstances, it simply pass N-th input to corresponding N-tn input of his parent GIC. It can be used for generation of wake-up events.

mmel: Tegra LIC is something special. It's not a cascaded (aka N: 1) but 'pass-through' (N:N)…
nwhitehornUnsubmitted
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My earlier inline comment didn't work, apparently.

Anyway, there's no need for special methods even in the fully general case of N:M routing with multiple parents. N:N shims are actually a particularly easy case that IBM likes putting in its POWER servers. This issue is unrelated to this diff, but it would be good to discuss this later in some better forum.

nwhitehorn: My earlier inline comment didn't work, apparently. Anyway, there's no need for special methods…
} }
static void static void
tegra_lic_disable_intr(device_t dev, struct intr_irqsrc *isrc) tegra_lic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
{ {
struct tegra_lic_sc *sc = device_get_softc(dev); struct tegra_lic_sc *sc = device_get_softc(dev);
PIC_DISABLE_INTR(sc->parent, isrc); PIC_DISABLE_INTR(sc->parent, isrc);
Show All 12 Linestegra_lic_map_intr(device_t dev, struct intr_map_data *data,
struct intr_irqsrc **isrcp) struct intr_irqsrc **isrcp)
{ {
struct tegra_lic_sc *sc = device_get_softc(dev); struct tegra_lic_sc *sc = device_get_softc(dev);
return (PIC_MAP_INTR(sc->parent, data, isrcp)); return (PIC_MAP_INTR(sc->parent, data, isrcp));
} }
static int static int
tegra_lic_release_intr(device_t dev, struct intr_irqsrc *isrc, tegra_lic_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
struct resource *res, struct intr_map_data *data) struct resource *res, struct intr_map_data *data)
{ {
struct tegra_lic_sc *sc = device_get_softc(dev); struct tegra_lic_sc *sc = device_get_softc(dev);
return (PIC_RELEASE_INTR(sc->parent, isrc, res, data)); return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
} }
static int static int
tegra_lic_setup_intr(device_t dev, struct intr_irqsrc *isrc, tegra_lic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
struct resource *res, struct intr_map_data *data) struct resource *res, struct intr_map_data *data)
{ {
struct tegra_lic_sc *sc = device_get_softc(dev); struct tegra_lic_sc *sc = device_get_softc(dev);
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} }
static device_method_t tegra_lic_methods[] = { static device_method_t tegra_lic_methods[] = {
DEVMETHOD(device_probe, tegra_lic_probe), DEVMETHOD(device_probe, tegra_lic_probe),
DEVMETHOD(device_attach, tegra_lic_attach), DEVMETHOD(device_attach, tegra_lic_attach),
DEVMETHOD(device_detach, tegra_lic_detach), DEVMETHOD(device_detach, tegra_lic_detach),
/* Interrupt controller interface */ /* Interrupt controller interface */
DEVMETHOD(pic_alloc_intr, tegra_lic_alloc_intr), DEVMETHOD(pic_activate_intr, tegra_lic_activate_intr),
DEVMETHOD(pic_disable_intr, tegra_lic_disable_intr), DEVMETHOD(pic_disable_intr, tegra_lic_disable_intr),
DEVMETHOD(pic_enable_intr, tegra_lic_enable_intr), DEVMETHOD(pic_enable_intr, tegra_lic_enable_intr),
DEVMETHOD(pic_map_intr, tegra_lic_map_intr), DEVMETHOD(pic_map_intr, tegra_lic_map_intr),
DEVMETHOD(pic_release_intr, tegra_lic_release_intr), DEVMETHOD(pic_deactivate_intr, tegra_lic_deactivate_intr),
DEVMETHOD(pic_setup_intr, tegra_lic_setup_intr), DEVMETHOD(pic_setup_intr, tegra_lic_setup_intr),
DEVMETHOD(pic_teardown_intr, tegra_lic_teardown_intr), DEVMETHOD(pic_teardown_intr, tegra_lic_teardown_intr),
DEVMETHOD(pic_pre_ithread, tegra_lic_pre_ithread), DEVMETHOD(pic_pre_ithread, tegra_lic_pre_ithread),
DEVMETHOD(pic_post_ithread, tegra_lic_post_ithread), DEVMETHOD(pic_post_ithread, tegra_lic_post_ithread),
DEVMETHOD(pic_post_filter, tegra_lic_post_filter), DEVMETHOD(pic_post_filter, tegra_lic_post_filter),
#ifdef SMP #ifdef SMP
DEVMETHOD(pic_bind_intr, tegra_lic_bind_intr), DEVMETHOD(pic_bind_intr, tegra_lic_bind_intr),
#endif #endif
DEVMETHOD_END DEVMETHOD_END
}; };
devclass_t tegra_lic_devclass; devclass_t tegra_lic_devclass;
DEFINE_CLASS_0(tegra_lic, tegra_lic_driver, tegra_lic_methods, DEFINE_CLASS_0(tegra_lic, tegra_lic_driver, tegra_lic_methods,
sizeof(struct tegra_lic_sc)); sizeof(struct tegra_lic_sc));
EARLY_DRIVER_MODULE(tegra_lic, simplebus, tegra_lic_driver, tegra_lic_devclass, EARLY_DRIVER_MODULE(tegra_lic, simplebus, tegra_lic_driver, tegra_lic_devclass,
NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1); NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1);