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sys/x86/iommu/intel_reg.h
| Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines | |||||
| #define DMAR_CTX1_T_PASS 8 /* Pass-Through */ | #define DMAR_CTX1_T_PASS 8 /* Pass-Through */ | ||||
| #define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address | #define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address | ||||
| Space Root */ | Space Root */ | ||||
| #define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */ | #define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */ | ||||
| #define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */ | #define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */ | ||||
| #define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */ | #define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */ | ||||
| #define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */ | #define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */ | ||||
| #define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */ | #define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */ | ||||
| #define DMAR_CTX2_DID_MASK 0xffff0 | |||||
| #define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */ | #define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */ | ||||
| #define DMAR_CTX2_GET_DID(ctx2) (((ctx2) & DMAR_CTX2_DID_MASK) >> 8) | |||||
| typedef struct dmar_pte { | typedef struct dmar_pte { | ||||
| uint64_t pte; | uint64_t pte; | ||||
| } dmar_pte_t; | } dmar_pte_t; | ||||
| #define DMAR_PTE_R 1 /* Read */ | #define DMAR_PTE_R 1 /* Read */ | ||||
| #define DMAR_PTE_W (1 << 1) /* Write */ | #define DMAR_PTE_W (1 << 1) /* Write */ | ||||
| #define DMAR_PTE_SP (1 << 7) /* Super Page */ | #define DMAR_PTE_SP (1 << 7) /* Super Page */ | ||||
| #define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */ | #define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */ | ||||
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| #define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */ | #define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */ | ||||
| #define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table | #define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table | ||||
| Pointer Status */ | Pointer Status */ | ||||
| #define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format | #define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format | ||||
| Interrupt Status */ | Interrupt Status */ | ||||
| /* Root-Entry Table Address register */ | /* Root-Entry Table Address register */ | ||||
| #define DMAR_RTADDR_REG 0x20 | #define DMAR_RTADDR_REG 0x20 | ||||
| #define DMAR_RTADDR_RTT (1 << 11) /* Root Table Type */ | |||||
| #define DMAR_RTADDR_RTA_MASK 0xfffffffffffff000 | |||||
| /* Context Command register */ | /* Context Command register */ | ||||
| #define DMAR_CCMD_REG 0x28 | #define DMAR_CCMD_REG 0x28 | ||||
| #define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */ | #define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */ | ||||
| #define DMAR_CCMD_ICC32 (1U << 31) | #define DMAR_CCMD_ICC32 (1U << 31) | ||||
| #define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation | #define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation | ||||
| Request Granularity */ | Request Granularity */ | ||||
| #define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */ | #define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */ | ||||
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