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sys/dev/ixl/i40e_nvm.c
Show First 20 Lines • Show All 214 Lines • ▼ Show 20 Lines | |||||
* | * | ||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, | enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, | ||||
u16 *data) | u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { | |||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | |||||
if (!ret_code) { | |||||
ret_code = i40e_read_nvm_word_aq(hw, offset, data); | |||||
i40e_release_nvm(hw); | |||||
} | |||||
} else { | |||||
ret_code = i40e_read_nvm_word_srctl(hw, offset, data); | ret_code = i40e_read_nvm_word_srctl(hw, offset, data); | ||||
} | |||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking | * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | ||||
* @data: word read from the Shadow RAM | * @data: word read from the Shadow RAM | ||||
* | * | ||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | ||||
**/ | **/ | ||||
enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw, | enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw, | ||||
u16 offset, | u16 offset, | ||||
u16 *data) | u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | |||||
ret_code = i40e_read_nvm_word_aq(hw, offset, data); | |||||
else | |||||
ret_code = i40e_read_nvm_word_srctl(hw, offset, data); | ret_code = i40e_read_nvm_word_srctl(hw, offset, data); | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register | * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | ||||
* @data: word read from the Shadow RAM | * @data: word read from the Shadow RAM | ||||
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines | |||||
* and followed by the release. | * and followed by the release. | ||||
**/ | **/ | ||||
enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw, | enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw, | ||||
u16 offset, | u16 offset, | ||||
u16 *words, u16 *data) | u16 *words, u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | |||||
ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data); | |||||
else | |||||
ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_buffer - Reads Shadow RAM buffer and acuire lock if necessary | * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acuire lock if necessary | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | ||||
* @words: (in) number of words to read; (out) number of words actually read | * @words: (in) number of words to read; (out) number of words actually read | ||||
* @data: words read from the Shadow RAM | * @data: words read from the Shadow RAM | ||||
* | * | ||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | ||||
* method. The buffer read is preceded by the NVM ownership take | * method. The buffer read is preceded by the NVM ownership take | ||||
* and followed by the release. | * and followed by the release. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, | enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, | ||||
u16 *words, u16 *data) | u16 *words, u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { | |||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | |||||
if (!ret_code) { | |||||
ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, | |||||
data); | |||||
i40e_release_nvm(hw); | |||||
} | |||||
} else { | |||||
ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | ||||
} | |||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register | * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | ||||
* @words: (in) number of words to read; (out) number of words actually read | * @words: (in) number of words to read; (out) number of words actually read | ||||
▲ Show 20 Lines • Show All 467 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw, | ||||
DEBUGFUNC("i40e_nvmupd_command"); | DEBUGFUNC("i40e_nvmupd_command"); | ||||
/* assume success */ | /* assume success */ | ||||
*perrno = 0; | *perrno = 0; | ||||
/* early check for status command and debug msgs */ | /* early check for status command and debug msgs */ | ||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); | upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); | ||||
i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", | i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", | ||||
i40e_nvm_update_state_str[upd_cmd], | i40e_nvm_update_state_str[upd_cmd], | ||||
hw->nvmupd_state, | hw->nvmupd_state, | ||||
hw->aq.nvm_release_on_done, | hw->nvm_release_on_done, hw->nvm_wait_opcode, | ||||
cmd->command, cmd->config, cmd->offset, cmd->data_size); | cmd->command, cmd->config, cmd->offset, cmd->data_size); | ||||
if (upd_cmd == I40E_NVMUPD_INVALID) { | if (upd_cmd == I40E_NVMUPD_INVALID) { | ||||
*perrno = -EFAULT; | *perrno = -EFAULT; | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"i40e_nvmupd_validate_command returns %d errno %d\n", | "i40e_nvmupd_validate_command returns %d errno %d\n", | ||||
upd_cmd, *perrno); | upd_cmd, *perrno); | ||||
} | } | ||||
/* a status request returns immediately rather than | /* a status request returns immediately rather than | ||||
* going into the state machine | * going into the state machine | ||||
*/ | */ | ||||
if (upd_cmd == I40E_NVMUPD_STATUS) { | if (upd_cmd == I40E_NVMUPD_STATUS) { | ||||
if (!cmd->data_size) { | |||||
*perrno = -EFAULT; | |||||
return I40E_ERR_BUF_TOO_SHORT; | |||||
} | |||||
bytes[0] = hw->nvmupd_state; | bytes[0] = hw->nvmupd_state; | ||||
if (cmd->data_size >= 4) { | |||||
bytes[1] = 0; | |||||
*((u16 *)&bytes[2]) = hw->nvm_wait_opcode; | |||||
} | |||||
return I40E_SUCCESS; | return I40E_SUCCESS; | ||||
} | } | ||||
switch (hw->nvmupd_state) { | switch (hw->nvmupd_state) { | ||||
case I40E_NVMUPD_STATE_INIT: | case I40E_NVMUPD_STATE_INIT: | ||||
status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); | status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_READING: | case I40E_NVMUPD_STATE_READING: | ||||
status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); | status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_WRITING: | case I40E_NVMUPD_STATE_WRITING: | ||||
status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); | status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_INIT_WAIT: | case I40E_NVMUPD_STATE_INIT_WAIT: | ||||
case I40E_NVMUPD_STATE_WRITE_WAIT: | case I40E_NVMUPD_STATE_WRITE_WAIT: | ||||
/* if we need to stop waiting for an event, clear | |||||
* the wait info and return before doing anything else | |||||
*/ | |||||
if (cmd->offset == 0xffff) { | |||||
i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode); | |||||
return I40E_SUCCESS; | |||||
} | |||||
status = I40E_ERR_NOT_READY; | status = I40E_ERR_NOT_READY; | ||||
*perrno = -EBUSY; | *perrno = -EBUSY; | ||||
break; | break; | ||||
default: | default: | ||||
/* invalid state, should never happen */ | /* invalid state, should never happen */ | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"NVMUPD: no such state %d\n", hw->nvmupd_state); | "NVMUPD: no such state %d\n", hw->nvmupd_state); | ||||
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines | case I40E_NVMUPD_WRITE_ERA: | ||||
if (status) { | if (status) { | ||||
*perrno = i40e_aq_rc_to_posix(status, | *perrno = i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status); | hw->aq.asq_last_status); | ||||
} else { | } else { | ||||
status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); | status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); | ||||
if (status) { | if (status) { | ||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
} else { | } else { | ||||
hw->aq.nvm_release_on_done = TRUE; | hw->nvm_release_on_done = TRUE; | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | ||||
} | } | ||||
} | } | ||||
break; | break; | ||||
case I40E_NVMUPD_WRITE_SA: | case I40E_NVMUPD_WRITE_SA: | ||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); | status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); | ||||
if (status) { | if (status) { | ||||
*perrno = i40e_aq_rc_to_posix(status, | *perrno = i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status); | hw->aq.asq_last_status); | ||||
} else { | } else { | ||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | ||||
if (status) { | if (status) { | ||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
} else { | } else { | ||||
hw->aq.nvm_release_on_done = TRUE; | hw->nvm_release_on_done = TRUE; | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | ||||
} | } | ||||
} | } | ||||
break; | break; | ||||
case I40E_NVMUPD_WRITE_SNT: | case I40E_NVMUPD_WRITE_SNT: | ||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); | status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); | ||||
if (status) { | if (status) { | ||||
*perrno = i40e_aq_rc_to_posix(status, | *perrno = i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status); | hw->aq.asq_last_status); | ||||
} else { | } else { | ||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | ||||
if (status) | if (status) { | ||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
else | } else { | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; | ||||
} | } | ||||
} | |||||
break; | break; | ||||
case I40E_NVMUPD_CSUM_SA: | case I40E_NVMUPD_CSUM_SA: | ||||
status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); | status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); | ||||
if (status) { | if (status) { | ||||
*perrno = i40e_aq_rc_to_posix(status, | *perrno = i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status); | hw->aq.asq_last_status); | ||||
} else { | } else { | ||||
status = i40e_update_nvm_checksum(hw); | status = i40e_update_nvm_checksum(hw); | ||||
if (status) { | if (status) { | ||||
*perrno = hw->aq.asq_last_status ? | *perrno = hw->aq.asq_last_status ? | ||||
i40e_aq_rc_to_posix(status, | i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status) : | hw->aq.asq_last_status) : | ||||
-EIO; | -EIO; | ||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
} else { | } else { | ||||
hw->aq.nvm_release_on_done = TRUE; | hw->nvm_release_on_done = TRUE; | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | ||||
} | } | ||||
} | } | ||||
break; | break; | ||||
case I40E_NVMUPD_EXEC_AQ: | case I40E_NVMUPD_EXEC_AQ: | ||||
status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); | status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | static enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw, | ||||
DEBUGFUNC("i40e_nvmupd_state_writing"); | DEBUGFUNC("i40e_nvmupd_state_writing"); | ||||
upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); | upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); | ||||
retry: | retry: | ||||
switch (upd_cmd) { | switch (upd_cmd) { | ||||
case I40E_NVMUPD_WRITE_CON: | case I40E_NVMUPD_WRITE_CON: | ||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | ||||
if (!status) | if (!status) { | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; | ||||
} | |||||
break; | break; | ||||
case I40E_NVMUPD_WRITE_LCB: | case I40E_NVMUPD_WRITE_LCB: | ||||
status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); | ||||
if (status) { | if (status) { | ||||
*perrno = hw->aq.asq_last_status ? | *perrno = hw->aq.asq_last_status ? | ||||
i40e_aq_rc_to_posix(status, | i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status) : | hw->aq.asq_last_status) : | ||||
-EIO; | -EIO; | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | ||||
} else { | } else { | ||||
hw->aq.nvm_release_on_done = TRUE; | hw->nvm_release_on_done = TRUE; | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | ||||
} | } | ||||
break; | break; | ||||
case I40E_NVMUPD_CSUM_CON: | case I40E_NVMUPD_CSUM_CON: | ||||
/* Assumes the caller has acquired the nvm */ | /* Assumes the caller has acquired the nvm */ | ||||
status = i40e_update_nvm_checksum(hw); | status = i40e_update_nvm_checksum(hw); | ||||
if (status) { | if (status) { | ||||
*perrno = hw->aq.asq_last_status ? | *perrno = hw->aq.asq_last_status ? | ||||
i40e_aq_rc_to_posix(status, | i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status) : | hw->aq.asq_last_status) : | ||||
-EIO; | -EIO; | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | ||||
} else { | } else { | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; | ||||
} | } | ||||
break; | break; | ||||
case I40E_NVMUPD_CSUM_LCB: | case I40E_NVMUPD_CSUM_LCB: | ||||
/* Assumes the caller has acquired the nvm */ | /* Assumes the caller has acquired the nvm */ | ||||
status = i40e_update_nvm_checksum(hw); | status = i40e_update_nvm_checksum(hw); | ||||
if (status) { | if (status) { | ||||
*perrno = hw->aq.asq_last_status ? | *perrno = hw->aq.asq_last_status ? | ||||
i40e_aq_rc_to_posix(status, | i40e_aq_rc_to_posix(status, | ||||
hw->aq.asq_last_status) : | hw->aq.asq_last_status) : | ||||
-EIO; | -EIO; | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | ||||
} else { | } else { | ||||
hw->aq.nvm_release_on_done = TRUE; | hw->nvm_release_on_done = TRUE; | ||||
hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | ||||
} | } | ||||
break; | break; | ||||
default: | default: | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"NVMUPD: bad cmd %s in writing state.\n", | "NVMUPD: bad cmd %s in writing state.\n", | ||||
i40e_nvm_update_state_str[upd_cmd]); | i40e_nvm_update_state_str[upd_cmd]); | ||||
Show All 33 Lines | if (gtime >= hw->nvm.hw_semaphore_timeout) { | ||||
} | } | ||||
} | } | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_nvmupd_check_wait_event - handle NVM update operation events | |||||
* @hw: pointer to the hardware structure | |||||
* @opcode: the event that just happened | |||||
**/ | |||||
void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode) | |||||
{ | |||||
if (opcode == hw->nvm_wait_opcode) { | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"NVMUPD: clearing wait on opcode 0x%04x\n", opcode); | |||||
if (hw->nvm_release_on_done) { | |||||
i40e_release_nvm(hw); | |||||
hw->nvm_release_on_done = FALSE; | |||||
} | |||||
hw->nvm_wait_opcode = 0; | |||||
switch (hw->nvmupd_state) { | |||||
case I40E_NVMUPD_STATE_INIT_WAIT: | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | |||||
break; | |||||
case I40E_NVMUPD_STATE_WRITE_WAIT: | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; | |||||
break; | |||||
default: | |||||
break; | |||||
} | |||||
} | |||||
} | |||||
/** | |||||
* i40e_nvmupd_validate_command - Validate given command | * i40e_nvmupd_validate_command - Validate given command | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @cmd: pointer to nvm update command buffer | * @cmd: pointer to nvm update command buffer | ||||
* @perrno: pointer to return error code | * @perrno: pointer to return error code | ||||
* | * | ||||
* Return one of the valid command types or I40E_NVMUPD_INVALID | * Return one of the valid command types or I40E_NVMUPD_INVALID | ||||
**/ | **/ | ||||
static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, | static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, | ||||
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines | static enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw, | ||||
status = i40e_asq_send_command(hw, aq_desc, buff, | status = i40e_asq_send_command(hw, aq_desc, buff, | ||||
buff_size, &cmd_details); | buff_size, &cmd_details); | ||||
if (status) { | if (status) { | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"i40e_nvmupd_exec_aq err %s aq_err %s\n", | "i40e_nvmupd_exec_aq err %s aq_err %s\n", | ||||
i40e_stat_str(hw, status), | i40e_stat_str(hw, status), | ||||
i40e_aq_str(hw, hw->aq.asq_last_status)); | i40e_aq_str(hw, hw->aq.asq_last_status)); | ||||
*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); | *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); | ||||
} | |||||
/* should we wait for a followup event? */ | |||||
if (cmd->offset) { | |||||
hw->nvm_wait_opcode = cmd->offset; | |||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | |||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq | * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
▲ Show 20 Lines • Show All 185 Lines • Show Last 20 Lines |