Changeset View
Changeset View
Standalone View
Standalone View
sys/dev/ixl/i40e_adminq_cmd.h
| Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines | enum i40e_admin_queue_opc { | ||||
| /* resource ownership */ | /* resource ownership */ | ||||
| i40e_aqc_opc_request_resource = 0x0008, | i40e_aqc_opc_request_resource = 0x0008, | ||||
| i40e_aqc_opc_release_resource = 0x0009, | i40e_aqc_opc_release_resource = 0x0009, | ||||
| i40e_aqc_opc_list_func_capabilities = 0x000A, | i40e_aqc_opc_list_func_capabilities = 0x000A, | ||||
| i40e_aqc_opc_list_dev_capabilities = 0x000B, | i40e_aqc_opc_list_dev_capabilities = 0x000B, | ||||
| /* Proxy commands */ | |||||
| i40e_aqc_opc_set_proxy_config = 0x0104, | |||||
| i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, | |||||
| /* LAA */ | /* LAA */ | ||||
| i40e_aqc_opc_mac_address_read = 0x0107, | i40e_aqc_opc_mac_address_read = 0x0107, | ||||
| i40e_aqc_opc_mac_address_write = 0x0108, | i40e_aqc_opc_mac_address_write = 0x0108, | ||||
| /* PXE */ | /* PXE */ | ||||
| i40e_aqc_opc_clear_pxe_mode = 0x0110, | i40e_aqc_opc_clear_pxe_mode = 0x0110, | ||||
| /* WoL commands */ | |||||
| i40e_aqc_opc_set_wol_filter = 0x0120, | |||||
| i40e_aqc_opc_get_wake_reason = 0x0121, | |||||
| /* internal switch commands */ | /* internal switch commands */ | ||||
| i40e_aqc_opc_get_switch_config = 0x0200, | i40e_aqc_opc_get_switch_config = 0x0200, | ||||
| i40e_aqc_opc_add_statistics = 0x0201, | i40e_aqc_opc_add_statistics = 0x0201, | ||||
| i40e_aqc_opc_remove_statistics = 0x0202, | i40e_aqc_opc_remove_statistics = 0x0202, | ||||
| i40e_aqc_opc_set_port_parameters = 0x0203, | i40e_aqc_opc_set_port_parameters = 0x0203, | ||||
| i40e_aqc_opc_get_switch_resource_alloc = 0x0204, | i40e_aqc_opc_get_switch_resource_alloc = 0x0204, | ||||
| i40e_aqc_opc_set_switch_config = 0x0205, | i40e_aqc_opc_set_switch_config = 0x0205, | ||||
| i40e_aqc_opc_rx_ctl_reg_read = 0x0206, | i40e_aqc_opc_rx_ctl_reg_read = 0x0206, | ||||
| Show All 22 Lines | enum i40e_admin_queue_opc { | ||||
| i40e_aqc_opc_remove_tag = 0x0256, | i40e_aqc_opc_remove_tag = 0x0256, | ||||
| i40e_aqc_opc_add_multicast_etag = 0x0257, | i40e_aqc_opc_add_multicast_etag = 0x0257, | ||||
| i40e_aqc_opc_remove_multicast_etag = 0x0258, | i40e_aqc_opc_remove_multicast_etag = 0x0258, | ||||
| i40e_aqc_opc_update_tag = 0x0259, | i40e_aqc_opc_update_tag = 0x0259, | ||||
| i40e_aqc_opc_add_control_packet_filter = 0x025A, | i40e_aqc_opc_add_control_packet_filter = 0x025A, | ||||
| i40e_aqc_opc_remove_control_packet_filter = 0x025B, | i40e_aqc_opc_remove_control_packet_filter = 0x025B, | ||||
| i40e_aqc_opc_add_cloud_filters = 0x025C, | i40e_aqc_opc_add_cloud_filters = 0x025C, | ||||
| i40e_aqc_opc_remove_cloud_filters = 0x025D, | i40e_aqc_opc_remove_cloud_filters = 0x025D, | ||||
| i40e_aqc_opc_clear_wol_switch_filters = 0x025E, | |||||
| i40e_aqc_opc_add_mirror_rule = 0x0260, | i40e_aqc_opc_add_mirror_rule = 0x0260, | ||||
| i40e_aqc_opc_delete_mirror_rule = 0x0261, | i40e_aqc_opc_delete_mirror_rule = 0x0261, | ||||
| /* DCB commands */ | /* DCB commands */ | ||||
| i40e_aqc_opc_dcb_ignore_pfc = 0x0301, | i40e_aqc_opc_dcb_ignore_pfc = 0x0301, | ||||
| i40e_aqc_opc_dcb_updated = 0x0302, | i40e_aqc_opc_dcb_updated = 0x0302, | ||||
| Show All 11 Lines | enum i40e_admin_queue_opc { | ||||
| i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, | i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, | ||||
| i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, | i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, | ||||
| i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, | i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, | ||||
| i40e_aqc_opc_query_port_ets_config = 0x0419, | i40e_aqc_opc_query_port_ets_config = 0x0419, | ||||
| i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, | i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, | ||||
| i40e_aqc_opc_suspend_port_tx = 0x041B, | i40e_aqc_opc_suspend_port_tx = 0x041B, | ||||
| i40e_aqc_opc_resume_port_tx = 0x041C, | i40e_aqc_opc_resume_port_tx = 0x041C, | ||||
| i40e_aqc_opc_configure_partition_bw = 0x041D, | i40e_aqc_opc_configure_partition_bw = 0x041D, | ||||
| /* hmc */ | /* hmc */ | ||||
| i40e_aqc_opc_query_hmc_resource_profile = 0x0500, | i40e_aqc_opc_query_hmc_resource_profile = 0x0500, | ||||
| i40e_aqc_opc_set_hmc_resource_profile = 0x0501, | i40e_aqc_opc_set_hmc_resource_profile = 0x0501, | ||||
| /* phy commands*/ | /* phy commands*/ | ||||
| i40e_aqc_opc_get_phy_abilities = 0x0600, | i40e_aqc_opc_get_phy_abilities = 0x0600, | ||||
| i40e_aqc_opc_set_phy_config = 0x0601, | i40e_aqc_opc_set_phy_config = 0x0601, | ||||
| i40e_aqc_opc_set_mac_config = 0x0603, | i40e_aqc_opc_set_mac_config = 0x0603, | ||||
| ▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines | enum i40e_admin_queue_opc { | ||||
| i40e_aqc_opc_lldp_start = 0x0A06, | i40e_aqc_opc_lldp_start = 0x0A06, | ||||
| i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, | i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, | ||||
| i40e_aqc_opc_lldp_set_local_mib = 0x0A08, | i40e_aqc_opc_lldp_set_local_mib = 0x0A08, | ||||
| i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, | i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, | ||||
| /* Tunnel commands */ | /* Tunnel commands */ | ||||
| i40e_aqc_opc_add_udp_tunnel = 0x0B00, | i40e_aqc_opc_add_udp_tunnel = 0x0B00, | ||||
| i40e_aqc_opc_del_udp_tunnel = 0x0B01, | i40e_aqc_opc_del_udp_tunnel = 0x0B01, | ||||
| i40e_aqc_opc_set_rss_key = 0x0B02, | |||||
| i40e_aqc_opc_set_rss_lut = 0x0B03, | |||||
| i40e_aqc_opc_get_rss_key = 0x0B04, | |||||
| i40e_aqc_opc_get_rss_lut = 0x0B05, | |||||
| /* Async Events */ | /* Async Events */ | ||||
| i40e_aqc_opc_event_lan_overflow = 0x1001, | i40e_aqc_opc_event_lan_overflow = 0x1001, | ||||
| /* OEM commands */ | /* OEM commands */ | ||||
| i40e_aqc_opc_oem_parameter_change = 0xFE00, | i40e_aqc_opc_oem_parameter_change = 0xFE00, | ||||
| i40e_aqc_opc_oem_device_status_change = 0xFE01, | i40e_aqc_opc_oem_device_status_change = 0xFE01, | ||||
| i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, | i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, | ||||
| ▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines | |||||
| #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 | #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 | ||||
| #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 | #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 | ||||
| #define I40E_AQ_CAP_ID_1588 0x0046 | #define I40E_AQ_CAP_ID_1588 0x0046 | ||||
| #define I40E_AQ_CAP_ID_IWARP 0x0051 | #define I40E_AQ_CAP_ID_IWARP 0x0051 | ||||
| #define I40E_AQ_CAP_ID_LED 0x0061 | #define I40E_AQ_CAP_ID_LED 0x0061 | ||||
| #define I40E_AQ_CAP_ID_SDP 0x0062 | #define I40E_AQ_CAP_ID_SDP 0x0062 | ||||
| #define I40E_AQ_CAP_ID_MDIO 0x0063 | #define I40E_AQ_CAP_ID_MDIO 0x0063 | ||||
| #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 | #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 | ||||
| #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 | |||||
| #define I40E_AQ_CAP_ID_FLEX10 0x00F1 | #define I40E_AQ_CAP_ID_FLEX10 0x00F1 | ||||
| #define I40E_AQ_CAP_ID_CEM 0x00F2 | #define I40E_AQ_CAP_ID_CEM 0x00F2 | ||||
| /* Set CPPM Configuration (direct 0x0103) */ | /* Set CPPM Configuration (direct 0x0103) */ | ||||
| struct i40e_aqc_cppm_configuration { | struct i40e_aqc_cppm_configuration { | ||||
| __le16 command_flags; | __le16 command_flags; | ||||
| #define I40E_AQ_CPPM_EN_LTRC 0x0800 | #define I40E_AQ_CPPM_EN_LTRC 0x0800 | ||||
| #define I40E_AQ_CPPM_EN_DMCTH 0x1000 | #define I40E_AQ_CPPM_EN_DMCTH 0x1000 | ||||
| #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 | #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 | ||||
| #define I40E_AQ_CPPM_EN_HPTC 0x4000 | #define I40E_AQ_CPPM_EN_HPTC 0x4000 | ||||
| #define I40E_AQ_CPPM_EN_DMARC 0x8000 | #define I40E_AQ_CPPM_EN_DMARC 0x8000 | ||||
| __le16 ttlx; | __le16 ttlx; | ||||
| __le32 dmacr; | __le32 dmacr; | ||||
| __le16 dmcth; | __le16 dmcth; | ||||
| u8 hptc; | u8 hptc; | ||||
| u8 reserved; | u8 reserved; | ||||
| __le32 pfltrc; | __le32 pfltrc; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); | I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); | ||||
| /* Set ARP Proxy command / response (indirect 0x0104) */ | /* Set ARP Proxy command / response (indirect 0x0104) */ | ||||
| struct i40e_aqc_arp_proxy_data { | struct i40e_aqc_arp_proxy_data { | ||||
| __le16 command_flags; | __le16 command_flags; | ||||
| #define I40E_AQ_ARP_INIT_IPV4 0x0008 | #define I40E_AQ_ARP_INIT_IPV4 0x0800 | ||||
| #define I40E_AQ_ARP_UNSUP_CTL 0x0010 | #define I40E_AQ_ARP_UNSUP_CTL 0x1000 | ||||
| #define I40E_AQ_ARP_ENA 0x0020 | #define I40E_AQ_ARP_ENA 0x2000 | ||||
| #define I40E_AQ_ARP_ADD_IPV4 0x0040 | #define I40E_AQ_ARP_ADD_IPV4 0x4000 | ||||
| #define I40E_AQ_ARP_DEL_IPV4 0x0080 | #define I40E_AQ_ARP_DEL_IPV4 0x8000 | ||||
| __le16 table_id; | __le16 table_id; | ||||
| __le32 pfpm_proxyfc; | __le32 enabled_offloads; | ||||
| #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 | |||||
| #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 | |||||
| __le32 ip_addr; | __le32 ip_addr; | ||||
| u8 mac_addr[6]; | u8 mac_addr[6]; | ||||
| u8 reserved[2]; | u8 reserved[2]; | ||||
| }; | }; | ||||
| I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); | I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); | ||||
| /* Set NS Proxy Table Entry Command (indirect 0x0105) */ | /* Set NS Proxy Table Entry Command (indirect 0x0105) */ | ||||
| struct i40e_aqc_ns_proxy_data { | struct i40e_aqc_ns_proxy_data { | ||||
| __le16 table_idx_mac_addr_0; | __le16 table_idx_mac_addr_0; | ||||
| __le16 table_idx_mac_addr_1; | __le16 table_idx_mac_addr_1; | ||||
| __le16 table_idx_ipv6_0; | __le16 table_idx_ipv6_0; | ||||
| __le16 table_idx_ipv6_1; | __le16 table_idx_ipv6_1; | ||||
| __le16 control; | __le16 control; | ||||
| #define I40E_AQ_NS_PROXY_ADD_0 0x0100 | #define I40E_AQ_NS_PROXY_ADD_0 0x0001 | ||||
| #define I40E_AQ_NS_PROXY_DEL_0 0x0200 | #define I40E_AQ_NS_PROXY_DEL_0 0x0002 | ||||
| #define I40E_AQ_NS_PROXY_ADD_1 0x0400 | #define I40E_AQ_NS_PROXY_ADD_1 0x0004 | ||||
| #define I40E_AQ_NS_PROXY_DEL_1 0x0800 | #define I40E_AQ_NS_PROXY_DEL_1 0x0008 | ||||
| #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 | #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 | ||||
| #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 | #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 | ||||
| #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 | #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 | ||||
| #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 | #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 | ||||
| #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 | #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 | ||||
| #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 | #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 | ||||
| #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 | #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 | ||||
| #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 | |||||
| #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 | |||||
| u8 mac_addr_0[6]; | u8 mac_addr_0[6]; | ||||
| u8 mac_addr_1[6]; | u8 mac_addr_1[6]; | ||||
| u8 local_mac_addr[6]; | u8 local_mac_addr[6]; | ||||
| u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ | u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ | ||||
| u8 ipv6_addr_1[16]; | u8 ipv6_addr_1[16]; | ||||
| }; | }; | ||||
| I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); | I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); | ||||
| Show All 33 Lines | struct i40e_aqc_mac_address_read_data { | ||||
| u8 pf_wol_mac[6]; | u8 pf_wol_mac[6]; | ||||
| }; | }; | ||||
| I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); | I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); | ||||
| /* Manage MAC Address Write Command (0x0108) */ | /* Manage MAC Address Write Command (0x0108) */ | ||||
| struct i40e_aqc_mac_address_write { | struct i40e_aqc_mac_address_write { | ||||
| __le16 command_flags; | __le16 command_flags; | ||||
| #define I40E_AQC_MC_MAG_EN 0x0100 | |||||
| #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 | #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 | ||||
| #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 | #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 | ||||
| #define I40E_AQC_WRITE_TYPE_PORT 0x8000 | #define I40E_AQC_WRITE_TYPE_PORT 0x8000 | ||||
| #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 | #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 | ||||
| #define I40E_AQC_WRITE_TYPE_MASK 0xC000 | #define I40E_AQC_WRITE_TYPE_MASK 0xC000 | ||||
| __le16 mac_sah; | __le16 mac_sah; | ||||
| __le32 mac_sal; | __le32 mac_sal; | ||||
| u8 reserved[8]; | u8 reserved[8]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); | I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); | ||||
| /* PXE commands (0x011x) */ | /* PXE commands (0x011x) */ | ||||
| /* Clear PXE Command and response (direct 0x0110) */ | /* Clear PXE Command and response (direct 0x0110) */ | ||||
| struct i40e_aqc_clear_pxe { | struct i40e_aqc_clear_pxe { | ||||
| u8 rx_cnt; | u8 rx_cnt; | ||||
| u8 reserved[15]; | u8 reserved[15]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); | I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); | ||||
| /* Set WoL Filter (0x0120) */ | |||||
| struct i40e_aqc_set_wol_filter { | |||||
| __le16 filter_index; | |||||
| #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 | |||||
| #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 | |||||
| #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ | |||||
| I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) | |||||
| #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 | |||||
| #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ | |||||
| I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) | |||||
| __le16 cmd_flags; | |||||
| #define I40E_AQC_SET_WOL_FILTER 0x8000 | |||||
| #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 | |||||
| #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 | |||||
| #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 | |||||
| __le16 valid_flags; | |||||
| #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 | |||||
| #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 | |||||
| u8 reserved[2]; | |||||
| __le32 address_high; | |||||
| __le32 address_low; | |||||
| }; | |||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); | |||||
| struct i40e_aqc_set_wol_filter_data { | |||||
| u8 filter[128]; | |||||
| u8 mask[16]; | |||||
| }; | |||||
| I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); | |||||
| /* Get Wake Reason (0x0121) */ | |||||
| struct i40e_aqc_get_wake_reason_completion { | |||||
| u8 reserved_1[2]; | |||||
| __le16 wake_reason; | |||||
| #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 | |||||
| #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ | |||||
| I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) | |||||
| #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 | |||||
| #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ | |||||
| I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) | |||||
| u8 reserved_2[12]; | |||||
| }; | |||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); | |||||
| /* Switch configuration commands (0x02xx) */ | /* Switch configuration commands (0x02xx) */ | ||||
| /* Used by many indirect commands that only pass an seid and a buffer in the | /* Used by many indirect commands that only pass an seid and a buffer in the | ||||
| * command | * command | ||||
| */ | */ | ||||
| struct i40e_aqc_switch_seid { | struct i40e_aqc_switch_seid { | ||||
| __le16 seid; | __le16 seid; | ||||
| u8 reserved[6]; | u8 reserved[6]; | ||||
| ▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines | |||||
| /* Set Port Parameters command (direct 0x0203) */ | /* Set Port Parameters command (direct 0x0203) */ | ||||
| struct i40e_aqc_set_port_parameters { | struct i40e_aqc_set_port_parameters { | ||||
| __le16 command_flags; | __le16 command_flags; | ||||
| #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 | #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 | ||||
| #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ | #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ | ||||
| #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 | #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 | ||||
| __le16 bad_frame_vsi; | __le16 bad_frame_vsi; | ||||
| #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 | |||||
| #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF | |||||
| __le16 default_seid; /* reserved for command */ | __le16 default_seid; /* reserved for command */ | ||||
| u8 reserved[10]; | u8 reserved[10]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); | ||||
| /* Get Switch Resource Allocation (indirect 0x0204) */ | /* Get Switch Resource Allocation (indirect 0x0204) */ | ||||
| struct i40e_aqc_get_switch_resource_alloc { | struct i40e_aqc_get_switch_resource_alloc { | ||||
| Show All 35 Lines | #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 | ||||
| u8 reserved2[6]; | u8 reserved2[6]; | ||||
| }; | }; | ||||
| I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); | I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); | ||||
| /* Set Switch Configuration (direct 0x0205) */ | /* Set Switch Configuration (direct 0x0205) */ | ||||
| struct i40e_aqc_set_switch_config { | struct i40e_aqc_set_switch_config { | ||||
| __le16 flags; | __le16 flags; | ||||
| /* flags used for both fields below */ | |||||
| #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 | #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 | ||||
| #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 | #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 | ||||
| __le16 valid_flags; | __le16 valid_flags; | ||||
| u8 reserved[12]; | u8 reserved[12]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); | ||||
| ▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines | |||||
| #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 | #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 | ||||
| #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ | #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ | ||||
| I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | ||||
| #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 | #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 | ||||
| #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ | #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ | ||||
| I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) | I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) | ||||
| /* queueing option section */ | /* queueing option section */ | ||||
| u8 queueing_opt_flags; | u8 queueing_opt_flags; | ||||
| #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 | |||||
| #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 | |||||
| #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 | #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 | ||||
| #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 | #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 | ||||
| #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 | |||||
| #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 | |||||
| u8 queueing_opt_reserved[3]; | u8 queueing_opt_reserved[3]; | ||||
| /* scheduler section */ | /* scheduler section */ | ||||
| u8 up_enable_bits; | u8 up_enable_bits; | ||||
| u8 sched_reserved; | u8 sched_reserved; | ||||
| /* outer up section */ | /* outer up section */ | ||||
| __le32 outer_up_table; /* same structure and defines as ingress tbl */ | __le32 outer_up_table; /* same structure and defines as ingress tbl */ | ||||
| u8 cmd_reserved[8]; | u8 cmd_reserved[8]; | ||||
| /* last 32 bytes are written by FW */ | /* last 32 bytes are written by FW */ | ||||
| ▲ Show 20 Lines • Show All 717 Lines • ▼ Show 20 Lines | struct i40e_aq_get_set_hmc_resource_profile { | ||||
| u8 pm_profile; | u8 pm_profile; | ||||
| u8 pe_vf_enabled; | u8 pe_vf_enabled; | ||||
| u8 reserved[14]; | u8 reserved[14]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); | I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); | ||||
| enum i40e_aq_hmc_profile { | enum i40e_aq_hmc_profile { | ||||
| /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ | /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ | ||||
| I40E_HMC_PROFILE_DEFAULT = 1, | I40E_HMC_PROFILE_DEFAULT = 1, | ||||
| I40E_HMC_PROFILE_FAVOR_VF = 2, | I40E_HMC_PROFILE_FAVOR_VF = 2, | ||||
| I40E_HMC_PROFILE_EQUAL = 3, | I40E_HMC_PROFILE_EQUAL = 3, | ||||
| }; | }; | ||||
| #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF | |||||
| #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F | |||||
| /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ | /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ | ||||
| /* set in param0 for get phy abilities to report qualified modules */ | /* set in param0 for get phy abilities to report qualified modules */ | ||||
| #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 | #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 | ||||
| #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 | #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 | ||||
| enum i40e_aq_phy_type { | enum i40e_aq_phy_type { | ||||
| I40E_PHY_TYPE_SGMII = 0x0, | I40E_PHY_TYPE_SGMII = 0x0, | ||||
| Show All 19 Lines | enum i40e_aq_phy_type { | ||||
| I40E_PHY_TYPE_10GBASE_CR1 = 0x17, | I40E_PHY_TYPE_10GBASE_CR1 = 0x17, | ||||
| I40E_PHY_TYPE_40GBASE_CR4 = 0x18, | I40E_PHY_TYPE_40GBASE_CR4 = 0x18, | ||||
| I40E_PHY_TYPE_40GBASE_SR4 = 0x19, | I40E_PHY_TYPE_40GBASE_SR4 = 0x19, | ||||
| I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, | I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, | ||||
| I40E_PHY_TYPE_1000BASE_SX = 0x1B, | I40E_PHY_TYPE_1000BASE_SX = 0x1B, | ||||
| I40E_PHY_TYPE_1000BASE_LX = 0x1C, | I40E_PHY_TYPE_1000BASE_LX = 0x1C, | ||||
| I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, | I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, | ||||
| I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, | I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, | ||||
| I40E_PHY_TYPE_25GBASE_KR = 0x1F, | |||||
| I40E_PHY_TYPE_25GBASE_CR = 0x20, | |||||
| I40E_PHY_TYPE_25GBASE_SR = 0x21, | |||||
| I40E_PHY_TYPE_25GBASE_LR = 0x22, | |||||
| I40E_PHY_TYPE_MAX | I40E_PHY_TYPE_MAX | ||||
| }; | }; | ||||
| #define I40E_LINK_SPEED_100MB_SHIFT 0x1 | #define I40E_LINK_SPEED_100MB_SHIFT 0x1 | ||||
| #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 | #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 | ||||
| #define I40E_LINK_SPEED_10GB_SHIFT 0x3 | #define I40E_LINK_SPEED_10GB_SHIFT 0x3 | ||||
| #define I40E_LINK_SPEED_40GB_SHIFT 0x4 | #define I40E_LINK_SPEED_40GB_SHIFT 0x4 | ||||
| #define I40E_LINK_SPEED_20GB_SHIFT 0x5 | #define I40E_LINK_SPEED_20GB_SHIFT 0x5 | ||||
| #define I40E_LINK_SPEED_25GB_SHIFT 0x6 | |||||
| enum i40e_aq_link_speed { | enum i40e_aq_link_speed { | ||||
| I40E_LINK_SPEED_UNKNOWN = 0, | I40E_LINK_SPEED_UNKNOWN = 0, | ||||
| I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), | I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), | ||||
| I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), | I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), | ||||
| I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), | I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), | ||||
| I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), | I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), | ||||
| I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) | I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), | ||||
| I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), | |||||
| }; | }; | ||||
| struct i40e_aqc_module_desc { | struct i40e_aqc_module_desc { | ||||
| u8 oui[3]; | u8 oui[3]; | ||||
| u8 reserved1; | u8 reserved1; | ||||
| u8 part_number[16]; | u8 part_number[16]; | ||||
| u8 revision[4]; | u8 revision[4]; | ||||
| u8 reserved2[8]; | u8 reserved2[8]; | ||||
| Show All 16 Lines | |||||
| #define I40E_AQ_EEE_1000BASE_T 0x0004 | #define I40E_AQ_EEE_1000BASE_T 0x0004 | ||||
| #define I40E_AQ_EEE_10GBASE_T 0x0008 | #define I40E_AQ_EEE_10GBASE_T 0x0008 | ||||
| #define I40E_AQ_EEE_1000BASE_KX 0x0010 | #define I40E_AQ_EEE_1000BASE_KX 0x0010 | ||||
| #define I40E_AQ_EEE_10GBASE_KX4 0x0020 | #define I40E_AQ_EEE_10GBASE_KX4 0x0020 | ||||
| #define I40E_AQ_EEE_10GBASE_KR 0x0040 | #define I40E_AQ_EEE_10GBASE_KR 0x0040 | ||||
| __le32 eeer_val; | __le32 eeer_val; | ||||
| u8 d3_lpan; | u8 d3_lpan; | ||||
| #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 | #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 | ||||
| u8 reserved[3]; | u8 phy_type_ext; | ||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 | |||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 | |||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 | |||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 | |||||
| u8 mod_type_ext; | |||||
| u8 ext_comp_code; | |||||
| u8 phy_id[4]; | u8 phy_id[4]; | ||||
| u8 module_type[3]; | u8 module_type[3]; | ||||
| u8 qualified_module_count; | u8 qualified_module_count; | ||||
| #define I40E_AQ_PHY_MAX_QMS 16 | #define I40E_AQ_PHY_MAX_QMS 16 | ||||
| struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; | struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; | ||||
| }; | }; | ||||
| I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); | I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); | ||||
| /* Set PHY Config (direct 0x0601) */ | /* Set PHY Config (direct 0x0601) */ | ||||
| struct i40e_aq_set_phy_config { /* same bits as above in all */ | struct i40e_aq_set_phy_config { /* same bits as above in all */ | ||||
| __le32 phy_type; | __le32 phy_type; | ||||
| u8 link_speed; | u8 link_speed; | ||||
| u8 abilities; | u8 abilities; | ||||
| /* bits 0-2 use the values from get_phy_abilities_resp */ | /* bits 0-2 use the values from get_phy_abilities_resp */ | ||||
| #define I40E_AQ_PHY_ENABLE_LINK 0x08 | #define I40E_AQ_PHY_ENABLE_LINK 0x08 | ||||
| #define I40E_AQ_PHY_ENABLE_AN 0x10 | #define I40E_AQ_PHY_ENABLE_AN 0x10 | ||||
| #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 | #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 | ||||
| __le16 eee_capability; | __le16 eee_capability; | ||||
| __le32 eeer; | __le32 eeer; | ||||
| u8 low_power_ctrl; | u8 low_power_ctrl; | ||||
| u8 reserved[3]; | u8 phy_type_ext; | ||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 | |||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 | |||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 | |||||
| #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 | |||||
| u8 reserved[2]; | |||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); | I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); | ||||
| /* Set MAC Config command data structure (direct 0x0603) */ | /* Set MAC Config command data structure (direct 0x0603) */ | ||||
| struct i40e_aq_set_mac_config { | struct i40e_aq_set_mac_config { | ||||
| __le16 max_frame_size; | __le16 max_frame_size; | ||||
| u8 params; | u8 params; | ||||
| ▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines | |||||
| #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 | #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 | ||||
| #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 | #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 | ||||
| #define I40E_AQ_LINK_TX_SHIFT 0x02 | #define I40E_AQ_LINK_TX_SHIFT 0x02 | ||||
| #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) | #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) | ||||
| #define I40E_AQ_LINK_TX_ACTIVE 0x00 | #define I40E_AQ_LINK_TX_ACTIVE 0x00 | ||||
| #define I40E_AQ_LINK_TX_DRAINED 0x01 | #define I40E_AQ_LINK_TX_DRAINED 0x01 | ||||
| #define I40E_AQ_LINK_TX_FLUSHED 0x03 | #define I40E_AQ_LINK_TX_FLUSHED 0x03 | ||||
| #define I40E_AQ_LINK_FORCED_40G 0x10 | #define I40E_AQ_LINK_FORCED_40G 0x10 | ||||
| /* 25G Error Codes */ | |||||
| #define I40E_AQ_25G_NO_ERR 0X00 | |||||
| #define I40E_AQ_25G_NOT_PRESENT 0X01 | |||||
| #define I40E_AQ_25G_NVM_CRC_ERR 0X02 | |||||
| #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 | |||||
| #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 | |||||
| #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 | |||||
| u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ | u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ | ||||
| __le16 max_frame_size; | __le16 max_frame_size; | ||||
| u8 config; | u8 config; | ||||
| #define I40E_AQ_CONFIG_CRC_ENA 0x04 | #define I40E_AQ_CONFIG_CRC_ENA 0x04 | ||||
| #define I40E_AQ_CONFIG_PACING_MASK 0x78 | #define I40E_AQ_CONFIG_PACING_MASK 0x78 | ||||
| u8 external_power_ability; | u8 power_desc; | ||||
| #define I40E_AQ_LINK_POWER_CLASS_1 0x00 | #define I40E_AQ_LINK_POWER_CLASS_1 0x00 | ||||
| #define I40E_AQ_LINK_POWER_CLASS_2 0x01 | #define I40E_AQ_LINK_POWER_CLASS_2 0x01 | ||||
| #define I40E_AQ_LINK_POWER_CLASS_3 0x02 | #define I40E_AQ_LINK_POWER_CLASS_3 0x02 | ||||
| #define I40E_AQ_LINK_POWER_CLASS_4 0x03 | #define I40E_AQ_LINK_POWER_CLASS_4 0x03 | ||||
| #define I40E_AQ_PWR_CLASS_MASK 0x03 | |||||
| u8 reserved[4]; | u8 reserved[4]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); | I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); | ||||
| /* Set event mask command (direct 0x613) */ | /* Set event mask command (direct 0x613) */ | ||||
| struct i40e_aqc_set_phy_int_mask { | struct i40e_aqc_set_phy_int_mask { | ||||
| u8 reserved[8]; | u8 reserved[8]; | ||||
| Show All 40 Lines | struct i40e_aqc_set_phy_debug { | ||||
| u8 command_flags; | u8 command_flags; | ||||
| #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 | #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 | ||||
| #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 | ||||
| #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ | ||||
| I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) | I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) | ||||
| #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 | ||||
| #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 | ||||
| #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 | #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 | ||||
| /* Disable link manageability on a single port */ | |||||
| #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 | #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 | ||||
| /* Disable link manageability on all ports needs both bits 4 and 5 */ | |||||
| #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 | |||||
| u8 reserved[15]; | u8 reserved[15]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); | ||||
| enum i40e_aq_phy_reg_type { | enum i40e_aq_phy_reg_type { | ||||
| I40E_AQC_PHY_REG_INTERNAL = 0x1, | I40E_AQC_PHY_REG_INTERNAL = 0x1, | ||||
| I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, | I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, | ||||
| ▲ Show 20 Lines • Show All 421 Lines • ▼ Show 20 Lines | struct i40e_aqc_del_udp_tunnel_completion { | ||||
| __le16 udp_port; | __le16 udp_port; | ||||
| u8 index; /* 0 to 15 */ | u8 index; /* 0 to 15 */ | ||||
| u8 multiple_pfs; | u8 multiple_pfs; | ||||
| u8 total_filters_used; | u8 total_filters_used; | ||||
| u8 reserved1[11]; | u8 reserved1[11]; | ||||
| }; | }; | ||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); | I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); | ||||
| struct i40e_aqc_get_set_rss_key { | |||||
| #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) | |||||
| #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 | |||||
| #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ | |||||
| I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) | |||||
| __le16 vsi_id; | |||||
| u8 reserved[6]; | |||||
| __le32 addr_high; | |||||
| __le32 addr_low; | |||||
| }; | |||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); | |||||
| struct i40e_aqc_get_set_rss_key_data { | |||||
| u8 standard_rss_key[0x28]; | |||||
| u8 extended_hash_key[0xc]; | |||||
| }; | |||||
| I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); | |||||
| struct i40e_aqc_get_set_rss_lut { | |||||
| #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) | |||||
| #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 | |||||
| #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ | |||||
| I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) | |||||
| __le16 vsi_id; | |||||
| #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 | |||||
| #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ | |||||
| I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) | |||||
| #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 | |||||
| #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 | |||||
| __le16 flags; | |||||
| u8 reserved[4]; | |||||
| __le32 addr_high; | |||||
| __le32 addr_low; | |||||
| }; | |||||
| I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); | |||||
| /* tunnel key structure 0x0B10 */ | /* tunnel key structure 0x0B10 */ | ||||
| struct i40e_aqc_tunnel_key_structure { | struct i40e_aqc_tunnel_key_structure { | ||||
| u8 key1_off; | u8 key1_off; | ||||
| u8 key2_off; | u8 key2_off; | ||||
| u8 key1_len; /* 0 to 15 */ | u8 key1_len; /* 0 to 15 */ | ||||
| u8 key2_len; /* 0 to 15 */ | u8 key2_len; /* 0 to 15 */ | ||||
| ▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines | |||||