Differential D56311 Diff 182690 sys/x86/include/specialreg.h

Changeset View

Standalone View

sys/x86/include/specialreg.h

	Show First 20 Lines • Show All 1,267 Lines • ▼ Show 20 Lines
	#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */			#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
	#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */			#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
	#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */			#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
	#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */			#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
	#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */			#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
	#define MSR_VM_CR 0xc0010114 /* SVM: feature control */			#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
	#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */			#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
	#define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */			#define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
				#define MSR_AMD_CPUID01 0xc0011004 /* CPUID 01 %ecx override */
				jhbUnsubmitted Not Done Inline Actions Is the comment correct? jhb: Is the comment correct?
				aokblastAuthorUnsubmitted Done Inline Actions Thanks! Fix it. aokblast: Thanks! Fix it.
	#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */			#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
	#define MSR_LS_CFG 0xc0011020			#define MSR_LS_CFG 0xc0011020
	#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */			#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
	#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */			#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */

	/* MSR_AMDK8_IPM */			/* MSR_AMDK8_IPM */
	#define AMDK8_SMIONCMPHALT (1ULL << 27)			#define AMDK8_SMIONCMPHALT (1ULL << 27)
	#define AMDK8_C1EONCMPHALT (1ULL << 28)			#define AMDK8_C1EONCMPHALT (1ULL << 28)
	▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines