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Differential D56919 Diff 177984 sys/x86/include/specialreg.h

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sys/x86/include/specialreg.h

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#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
/* MSR IA32_FLUSH_CMD */ /* MSR IA32_FLUSH_CMD */
#define IA32_FLUSH_CMD_L1D 0x00000001 #define IA32_FLUSH_CMD_L1D 0x00000001
/* MSR IA32_MCU_OPT_CTRL */ /* MSR IA32_MCU_OPT_CTRL */
#define IA32_RNGDS_MITG_DIS 0x00000001 #define IA32_RNGDS_MITG_DIS 0x00000001
/* MSR IA32_PM_ENABLE */
#define IA32_PM_ENABLE_HWP_ENABLE (1ULL << 0)
mchooUnsubmitted
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Like above, you can simply use 0x00000001,

mchoo: Like above, you can simply use `0x00000001`,
emasteUnsubmitted
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Values below are of the form (1ULL << x) though and I think it's fine.

From the Intel doc:

HWP_ENABLE (bit 0, R/W1Once) — Software sets this bit to enable HWP with autonomous selection. When set, the processor will disregard input from the legacy performance control interface (IA32_PERF_CTL). Note this bit can only be enabled once from the default value. Once set, writes to the HWP_ENABLE bit are ignored. Only RESET will clear this bit. Default = zero (0).

So if the source doc uses "bit 0" I think (1ULL << 0) is straightforward.

emaste: Values below are of the form `(1ULL << x)` though and I think it's fine. From the Intel doc: >…
/* MSR IA32_HWP_CAPABILITIES */ /* MSR IA32_HWP_CAPABILITIES */
#define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
#define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
#define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
#define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
/* MSR IA32_HWP_REQUEST */ /* MSR IA32_HWP_REQUEST */
#define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63)
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