Differential D50295 Diff 175765 sys/dev/ixgbe/ixgbe_x540.c

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sys/dev/ixgbe/ixgbe_x540.c

Show First 20 Lines • Show All 872 Lines • ▼ Show 20 Lines	if (mask & IXGBE_GSSR_I2C_MASK)
swmask \|= mask & IXGBE_GSSR_I2C_MASK;		swmask \|= mask & IXGBE_GSSR_I2C_MASK;
ixgbe_get_swfw_sync_semaphore(hw);		ixgbe_get_swfw_sync_semaphore(hw);

swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));		swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
swfw_sync &= ~swmask;		swfw_sync &= ~swmask;
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);		IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);

ixgbe_release_swfw_sync_semaphore(hw);		ixgbe_release_swfw_sync_semaphore(hw);
msec_delay(2);
		/*
		kgalazkaUnsubmitted Not Done Inline Actions I've found a vouge note that this delay was added to prevent some issue with link establishment after a HW reset. It doesn't explain though why it was needed here, instead of e.g. somewhere in ixgbe_reset_hw_X540. Let me dig a bit more. kgalazka: I've found a vouge note that this delay was added to prevent some issue with link establishment…
		adrianAuthorUnsubmitted Done Inline Actions thanks! have you found anything yet? Can you say which chipset(s) it was trying to fix? adrian: thanks! have you found anything yet? Can you say which chipset(s) it was trying to fix?
		* EEPROM / flash access requires a 2ms sleep or interacting with
		* them isn't stable. However, a 2ms delay for all sync operations
		* is very expensive for MDIO access.
		*
		* So use a 10us delay for PHY0/PHY1 MDIO and management access and
		* 2ms for everything else. This keep MDIO access (eg from a switch
		* driver) fast.
		*/
		if (mask &
		(IXGBE_GSSR_PHY0_SM \| IXGBE_GSSR_PHY1_SM \| IXGBE_GSSR_SW_MNG_SM))
		usec_delay(10);
		else
		usec_delay(2000);
}		}

/**		/**
* ixgbe_get_swfw_sync_semaphore - Get hardware semaphore		* ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
*		*
* Sets the hardware semaphores so SW/FW can gain control of shared resources		* Sets the hardware semaphores so SW/FW can gain control of shared resources
**/		**/
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