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Differential D55945 Diff 175434 sys/arm64/include/hypervisor.h

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sys/arm64/include/hypervisor.h

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#define SCTLR_EL2_I_SHIFT 12 #define SCTLR_EL2_I_SHIFT 12
#define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT)
#define SCTLR_EL2_WXN_SHIFT 19 #define SCTLR_EL2_WXN_SHIFT 19
#define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT)
#define SCTLR_EL2_EIS_SHIFT 22 #define SCTLR_EL2_EIS_SHIFT 22
#define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT)
#define SCTLR_EL2_EE_SHIFT 25 #define SCTLR_EL2_EE_SHIFT 25
#define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT)
#define SCTLR_EL2_ITFSB_SHIFT 37
#define SCTLR_EL2_ITFSB (0x1UL << SCTLR_EL2_ITFSB_SHIFT)
#define SCTLR_EL2_TCF0_SHIFT 38
#define SCTLR_EL2_TCF0 (0x2UL << SCTLR_EL2_TCF0_SHIFT)
#define SCTLR_EL2_TCF_SHIFT 40
#define SCTLR_EL2_TCF (0x2UL << SCTLR_EL2_TCF_SHIFT)
#define SCTLR_EL2_ATA0_SHIFT 42
#define SCTLR_EL2_ATA0 (0x1UL << SCTLR_EL2_ATA0_SHIFT)
#define SCTLR_EL2_ATA_SHIFT 43
#define SCTLR_EL2_ATA (0x1UL << SCTLR_EL2_ATA_SHIFT)
/* TCR_EL2 - Translation Control Register */ /* TCR_EL2 - Translation Control Register */
#define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23))
#define TCR_EL2_T0SZ_SHIFT 0 #define TCR_EL2_T0SZ_SHIFT 0
#define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT)
#define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT)
/* Bits 7:6 are reserved */ /* Bits 7:6 are reserved */
#define TCR_EL2_IRGN0_SHIFT 8 #define TCR_EL2_IRGN0_SHIFT 8
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#define TCR_EL2_HWU60_SHIFT 26 #define TCR_EL2_HWU60_SHIFT 26
#define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT)
#define TCR_EL2_HWU61_SHIFT 27 #define TCR_EL2_HWU61_SHIFT 27
#define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT)
#define TCR_EL2_HWU62_SHIFT 28 #define TCR_EL2_HWU62_SHIFT 28
#define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT)
#define TCR_EL2_HWU \ #define TCR_EL2_HWU \
(TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62)
#define TCR_EL2_TCMA_SHIFT 30
#define TCR_EL2_TCMA (1UL << TCR_EL2_TCMA_SHIFT)
/* TFSR_EL2 - Tag Fault Status Register EL2 */
#define TFSR_EL2_REG MRS_REG_ALT_NAME(TFSR_EL2)
#define TFSR_EL2_op0 3
#define TFSR_EL2_op1 4
#define TFSR_EL2_CRn 5
#define TFSR_EL2_CRm 6
#define TFSR_EL2_op2 0
#define TFSR_TF0_SHIFT 0
#define TFSR_TF0_MASK (UL(0x1) << TFSR_TF0_SHIFT)
#define TFSR_TF1_SHIFT 1
#define TFSR_TF1_MASK (UL(0x1) << TFSR_TF1_SHIFT)
/* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
#define VMPIDR_EL2_U 0x0000000040000000 #define VMPIDR_EL2_U 0x0000000040000000
#define VMPIDR_EL2_MT 0x0000000001000000 #define VMPIDR_EL2_MT 0x0000000001000000
#define VMPIDR_EL2_RES1 0x0000000080000000 #define VMPIDR_EL2_RES1 0x0000000080000000
/* VTCR_EL2 - Virtualization Translation Control Register */ /* VTCR_EL2 - Virtualization Translation Control Register */
#define VTCR_EL2_RES1 (0x1UL << 31) #define VTCR_EL2_RES1 (0x1UL << 31)
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