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sys/dev/bhnd/cores/chipc/chipcreg.h
| Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines | |||||
| #define CHIPC_SPROM_DATA 0x198 | #define CHIPC_SPROM_DATA 0x198 | ||||
| /* Clock control and hardware workarounds (corerev >= 20) */ | /* Clock control and hardware workarounds (corerev >= 20) */ | ||||
| #define CHIPC_CLK_CTL_ST 0x1E0 | #define CHIPC_CLK_CTL_ST 0x1E0 | ||||
| #define CHIPC_SPROM_HWWAR 0x19 | #define CHIPC_SPROM_HWWAR 0x19 | ||||
| #define CHIPC_UART_BASE 0x300 | #define CHIPC_UART_BASE 0x300 | ||||
| #define CHIPC_UART_SIZE 0x100 | #define CHIPC_UART_SIZE 0x100 | ||||
| #define CHIPC_UART0_BASE CHIPC_UART_BASE | #define CHIPC_UART_MAX 3 /**< max UART blocks */ | ||||
| #define CHIPC_UART1_BASE (CHIPC_UART_BASE + CHIPC_UART_SIZE) | #define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) | ||||
| /* PMU registers (rev >= 20) */ | /* PMU registers (rev >= 20) */ | ||||
| #define CHIPC_PMU_BASE 0x600 | #define CHIPC_PMU_BASE 0x600 | ||||
| #define CHIPC_PMU_SIZE 0x70 | #define CHIPC_PMU_SIZE 0x70 | ||||
| #define CHIPC_PMU_CTRL 0x600 | #define CHIPC_PMU_CTRL 0x600 | ||||
| #define CHIPC_PMU_CAP 0x604 | #define CHIPC_PMU_CAP 0x604 | ||||
| #define CHIPC_PMU_ST 0x608 | #define CHIPC_PMU_ST 0x608 | ||||
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