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sys/dev/bhnd/cores/chipc/chipc_spi.h
| Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines | |||||
| */ | */ | ||||
| #define CHIPC_SPI_FLASHCTL_CSACTIVE 0x00001000 | #define CHIPC_SPI_FLASHCTL_CSACTIVE 0x00001000 | ||||
| #define CHIPC_SPI_FLASHCTL_START 0x80000000 //same as BUSY | #define CHIPC_SPI_FLASHCTL_START 0x80000000 //same as BUSY | ||||
| #define CHIPC_SPI_FLASHCTL_BUSY 0x80000000 //same as BUSY | #define CHIPC_SPI_FLASHCTL_BUSY 0x80000000 //same as BUSY | ||||
| #define CHIPC_SPI_FLASHADDR 0x04 | #define CHIPC_SPI_FLASHADDR 0x04 | ||||
| #define CHIPC_SPI_FLASHDATA 0x08 | #define CHIPC_SPI_FLASHDATA 0x08 | ||||
| struct chipc_spi_softc { | struct chipc_spi_softc { | ||||
| device_t dev; | device_t sc_dev; | ||||
| struct resource *sc_res; /**< SPI registers */ | |||||
| int sc_rid; | |||||
| /* SPI registers */ | struct resource *sc_flash_res; /**< flash shadow */ | ||||
| struct resource *sc_mem_res; | int sc_flash_rid; | ||||
| /* MMIO flash */ | |||||
| struct resource *sc_res; | |||||
| }; | }; | ||||
| /* register space access macros */ | /* register space access macros */ | ||||
| #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ | #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_res, 0, 0, \ | ||||
| BUS_SPACE_BARRIER_WRITE) | BUS_SPACE_BARRIER_WRITE) | ||||
| #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ | #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_res, 0, 0, \ | ||||
| BUS_SPACE_BARRIER_READ) | BUS_SPACE_BARRIER_READ) | ||||
| #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ | #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_res, 0, 0, \ | ||||
| BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) | BUS_SPACE_BARRIER_READ | \ | ||||
| BUS_SPACE_BARRIER_WRITE) | |||||
| #define SPI_WRITE(sc, reg, val) do { \ | #define SPI_WRITE(sc, reg, val) bus_write_4(sc->sc_res, (reg), (val)); | ||||
| bus_write_4(sc->sc_mem_res, (reg), (val)); \ | |||||
| } while (0) | |||||
| #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) | #define SPI_READ(sc, reg) bus_read_4(sc->sc_res, (reg)) | ||||
| #define SPI_SET_BITS(sc, reg, bits) \ | #define SPI_SET_BITS(sc, reg, bits) \ | ||||
| SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) | SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) | ||||
| #define SPI_CLEAR_BITS(sc, reg, bits) \ | #define SPI_CLEAR_BITS(sc, reg, bits) \ | ||||
| SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) | SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) | ||||
| #endif /* _BHND_CORES_CHIPC_CHIPC_SPI_H_ */ | #endif /* _BHND_CORES_CHIPC_CHIPC_SPI_H_ */ | ||||