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Differential D54922 Diff 171129 sys/dev/rge/if_rge_hw.c

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sys/dev/rge/if_rge_hw.c

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
static void rge_ephy_config_mac_r25(struct rge_softc *sc); static void rge_ephy_config_mac_r25(struct rge_softc *sc);
static void rge_ephy_config_mac_r25b(struct rge_softc *sc); static void rge_ephy_config_mac_r25b(struct rge_softc *sc);
static void rge_ephy_config_mac_r27(struct rge_softc *sc); static void rge_ephy_config_mac_r27(struct rge_softc *sc);
static void rge_phy_config_mac_r27(struct rge_softc *sc); static void rge_phy_config_mac_r27(struct rge_softc *sc);
static void rge_phy_config_mac_r26_1(struct rge_softc *sc); static void rge_phy_config_mac_r26_1(struct rge_softc *sc);
static void rge_phy_config_mac_r26_2(struct rge_softc *sc); static void rge_phy_config_mac_r26_2(struct rge_softc *sc);
static void rge_phy_config_mac_r25(struct rge_softc *sc); static void rge_phy_config_mac_r25(struct rge_softc *sc);
static void rge_phy_config_mac_r25b(struct rge_softc *sc); static void rge_phy_config_mac_r25b(struct rge_softc *sc);
static void rge_phy_config_mac_r25d(struct rge_softc *sc); static void rge_phy_config_mac_r25d_1(struct rge_softc *);
static void rge_phy_config_mac_r25d_2(struct rge_softc *);
static void rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever); static void rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever);
static void rge_hw_init(struct rge_softc *sc); static void rge_hw_init(struct rge_softc *sc);
static void rge_disable_phy_ocp_pwrsave(struct rge_softc *sc); static void rge_disable_phy_ocp_pwrsave(struct rge_softc *sc);
static void rge_patch_phy_mcu(struct rge_softc *sc, int set); static void rge_patch_phy_mcu(struct rge_softc *sc, int set);
static void rge_disable_hw_im(struct rge_softc *sc); static void rge_disable_hw_im(struct rge_softc *sc);
static void rge_disable_sim_im(struct rge_softc *sc); static void rge_disable_sim_im(struct rge_softc *sc);
static void rge_setup_sim_im(struct rge_softc *sc); static void rge_setup_sim_im(struct rge_softc *sc);
static void rge_switch_mcu_ram_page(struct rge_softc *sc, int page); static void rge_switch_mcu_ram_page(struct rge_softc *sc, int page);
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines if (type == MAC_R25) {
rge_write_mac_ocp(sc, 0xfc42, 0x0e24); rge_write_mac_ocp(sc, 0xfc42, 0x0e24);
rge_write_mac_ocp(sc, 0xfc48, 0x307a); rge_write_mac_ocp(sc, 0xfc48, 0x307a);
} else if (type == MAC_R25B) { } else if (type == MAC_R25B) {
rge_switch_mcu_ram_page(sc, 0); rge_switch_mcu_ram_page(sc, 0);
for (i = 0; i < nitems(rtl8125b_mac_bps); i++) { for (i = 0; i < nitems(rtl8125b_mac_bps); i++) {
rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
rtl8125b_mac_bps[i].val); rtl8125b_mac_bps[i].val);
} }
} else if (type == MAC_R25D) { } else if (type == MAC_R25D_1) {
for (npages = 0; npages < 3; npages++) { for (npages = 0; npages < 3; npages++) {
rge_switch_mcu_ram_page(sc, npages); rge_switch_mcu_ram_page(sc, npages);
rge_write_mac_ocp(sc, 0xf800, rge_write_mac_ocp(sc, 0xf800,
(npages == 0) ? 0xe002 : 0); (npages == 0) ? 0xe002 : 0);
rge_write_mac_ocp(sc, 0xf802, rge_write_mac_ocp(sc, 0xf802,
(npages == 0) ? 0xe006 : 0); (npages == 0) ? 0xe006 : 0);
rge_write_mac_ocp(sc, 0xf804, rge_write_mac_ocp(sc, 0xf804,
Show All 21 Lines for (npages = 0; npages < 3; npages++) {
rge_write_mac_ocp(sc, 0xf9fc, rge_write_mac_ocp(sc, 0xf9fc,
(npages == 2) ? 0x0217 : 0); (npages == 2) ? 0x0217 : 0);
rge_write_mac_ocp(sc, 0xf9fe, rge_write_mac_ocp(sc, 0xf9fe,
(npages == 2) ? 0x0d2a : 0); (npages == 2) ? 0x0d2a : 0);
} }
rge_write_mac_ocp(sc, 0xfc26, 0x8000); rge_write_mac_ocp(sc, 0xfc26, 0x8000);
rge_write_mac_ocp(sc, 0xfc28, 0x14a2); rge_write_mac_ocp(sc, 0xfc28, 0x14a2);
rge_write_mac_ocp(sc, 0xfc48, 0x0001); rge_write_mac_ocp(sc, 0xfc48, 0x0001);
} else if (type == MAC_R25D_2) {
for (npages = 0; npages < 3; npages++) {
rge_switch_mcu_ram_page(sc, npages);
for (i = 0; i < nitems(rtl8125d_2_mac_bps); i++) {
if (npages == 0)
rge_write_mac_ocp(sc,
rtl8125d_2_mac_bps[i].reg,
rtl8125d_2_mac_bps[i].val);
else
rge_write_mac_ocp(sc,
rtl8125d_2_mac_bps[i].reg, 0);
} }
for (reg = 0xf884; reg <= 0xf9f6; reg += 2)
rge_write_mac_ocp(sc, reg, 0);
rge_write_mac_ocp(sc, 0xf9f8,
(npages == 2) ? 0x6938 : 0);
rge_write_mac_ocp(sc, 0xf9fa,
(npages == 2) ? 0x0a19: 0);
rge_write_mac_ocp(sc, 0xf9fc,
(npages == 2) ? 0x030e: 0);
rge_write_mac_ocp(sc, 0xf9fe,
(npages == 2) ? 0x0b2f: 0);
} }
rge_write_mac_ocp(sc, 0xfc26, 0x8000);
rge_write_mac_ocp(sc, 0xfc28, 0x2382);
rge_write_mac_ocp(sc, 0xfc48, 0x0001);
}
}
void void
rge_mac_config_ext_mcu(struct rge_softc *sc, enum rge_mac_type type) rge_mac_config_ext_mcu(struct rge_softc *sc, enum rge_mac_type type)
{ {
const struct rge_mac_bps *bps; const struct rge_mac_bps *bps;
uint64_t mcodever = 0; uint64_t mcodever = 0;
int i; int i;
Show All 14 Lines if (sc->rge_mcodever != mcodever) {
/* Switch to page 0. */ /* Switch to page 0. */
rge_switch_mcu_ram_page(sc, 0); rge_switch_mcu_ram_page(sc, 0);
for (i = 0; i < bps->count; i++) for (i = 0; i < bps->count; i++)
rge_write_mac_ocp(sc, bps->regs[i], rge_write_mac_ocp(sc, bps->regs[i],
bps->vals[i]); bps->vals[i]);
} }
rge_write_mac_ocp(sc, 0xfc26, 0x8000); rge_write_mac_ocp(sc, 0xfc26, 0x8000);
rge_write_mac_ocp(sc, 0xfc2c, 0x2360); rge_write_mac_ocp(sc, 0xfc2c, 0x2360);
rge_write_mac_ocp(sc, 0xfc2E, 0x14a4); rge_write_mac_ocp(sc, 0xfc2e, 0x14a4);
rge_write_mac_ocp(sc, 0xfc30, 0x415e); rge_write_mac_ocp(sc, 0xfc30, 0x415e);
rge_write_mac_ocp(sc, 0xfc32, 0x41e4); rge_write_mac_ocp(sc, 0xfc32, 0x41e4);
rge_write_mac_ocp(sc, 0xfc34, 0x4280); rge_write_mac_ocp(sc, 0xfc34, 0x4280);
rge_write_mac_ocp(sc, 0xfc36, 0x234a); rge_write_mac_ocp(sc, 0xfc36, 0x234a);
rge_write_mac_ocp(sc, 0xfc48, 0x00fc); rge_write_mac_ocp(sc, 0xfc48, 0x00fc);
} else if (type == MAC_R26_2) { } else if (type == MAC_R26_2) {
bps = &rtl8126_2_mac_bps; bps = &rtl8126_2_mac_bps;
mcodever = mcodever =
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Linesrge_phy_config(struct rge_softc *sc)
switch (sc->rge_type) { switch (sc->rge_type) {
case MAC_R25: case MAC_R25:
rge_phy_config_mac_r25(sc); rge_phy_config_mac_r25(sc);
break; break;
case MAC_R25B: case MAC_R25B:
rge_phy_config_mac_r25b(sc); rge_phy_config_mac_r25b(sc);
break; break;
case MAC_R25D: case MAC_R25D_1:
rge_phy_config_mac_r25d(sc); rge_phy_config_mac_r25d_1(sc);
break; break;
case MAC_R25D_2:
rge_phy_config_mac_r25d_2(sc);
break;
case MAC_R26_1: case MAC_R26_1:
rge_phy_config_mac_r26_1(sc); rge_phy_config_mac_r26_1(sc);
break; break;
case MAC_R26_2: case MAC_R26_2:
rge_phy_config_mac_r26_2(sc); rge_phy_config_mac_r26_2(sc);
break; break;
case MAC_R27: case MAC_R27:
rge_phy_config_mac_r27(sc); rge_phy_config_mac_r27(sc);
break; break;
default: default:
break; /* Can't happen. */ break; /* Can't happen. */
} }
RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000);
/* Disable EEE. */ /* Disable EEE. */
RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
if (sc->rge_type == MAC_R25) { if (sc->rge_type == MAC_R25) {
RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
} else if (sc->rge_type == MAC_R25B || sc->rge_type == MAC_R25D) } else if (sc->rge_type == MAC_R25B || RGE_TYPE_R25D(sc))
RGE_PHY_SETBIT(sc, 0xa432, 0x0010); RGE_PHY_SETBIT(sc, 0xa432, 0x0010);
RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006); RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006);
RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27)
RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002); RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002);
RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
▲ Show 20 Lines • Show All 815 Lines • ▼ Show 20 Linesrge_phy_config_mac_r25b(struct rge_softc *sc)
rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
rge_write_phy_ocp(sc, 0xa436, 0x8170); rge_write_phy_ocp(sc, 0xa436, 0x8170);
val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700;
rge_write_phy_ocp(sc, 0xa438, val | 0xd800); rge_write_phy_ocp(sc, 0xa438, val | 0xd800);
RGE_PHY_SETBIT(sc, 0xa424, 0x0008); RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
} }
static void static void
rge_phy_config_mac_r25d(struct rge_softc *sc) rge_phy_config_mac_r25d_1(struct rge_softc *sc)
{ {
uint16_t val; uint16_t val;
int i; int i;
rge_phy_config_mcu(sc, RGE_MAC_R25D_RCODE_VER); rge_phy_config_mcu(sc, RGE_MAC_R25D_1_RCODE_VER);
RGE_PHY_SETBIT(sc, 0xa442, 0x0800); RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
rge_patch_phy_mcu(sc, 1); rge_patch_phy_mcu(sc, 1);
RGE_PHY_SETBIT(sc, 0xbf96, 0x8000); RGE_PHY_SETBIT(sc, 0xbf96, 0x8000);
val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007; val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007;
rge_write_phy_ocp(sc, 0xbf94, val | 0x0005); rge_write_phy_ocp(sc, 0xbf94, val | 0x0005);
val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00; val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00;
▲ Show 20 Lines • Show All 171 Lines • ▼ Show 20 Linesrge_phy_config_mac_r25d_1(struct rge_softc *sc)
RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000); RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000);
RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020);
RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
RGE_PHY_SETBIT(sc, 0xa430, 0x1001); RGE_PHY_SETBIT(sc, 0xa430, 0x1001);
RGE_PHY_SETBIT(sc, 0xa442, 0x0080); RGE_PHY_SETBIT(sc, 0xa442, 0x0080);
} }
static void static void
rge_phy_config_mac_r25d_2(struct rge_softc *sc)
{
uint16_t val;
rge_phy_config_mcu(sc, RGE_MAC_R25D_2_RCODE_VER);
RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
rge_patch_phy_mcu(sc, 1);
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000);
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
rge_write_phy_ocp(sc, 0xbc80, val | 0x0004);
RGE_PHY_SETBIT(sc, 0xbc82, 0xe000);
RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00);
val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
rge_write_phy_ocp(sc, 0xbc80, val | 0x0005);
val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0;
rge_write_phy_ocp(sc, 0xbc82, val | 0x0040);
RGE_PHY_SETBIT(sc, 0xbc82, 0x001c);
RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000);
RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
rge_patch_phy_mcu(sc, 0);
val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc;
rge_write_phy_ocp(sc, 0xac7e, val | 0x00b4);
rge_write_phy_ocp(sc, 0xb87c, 0x8105);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00);
rge_write_phy_ocp(sc, 0xb87c, 0x8117);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00);
rge_write_phy_ocp(sc, 0xb87c, 0x8103);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0x7400);
rge_write_phy_ocp(sc, 0xb87c, 0x8115);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0x3400);
rge_write_phy_ocp(sc, 0xb87c, 0x8feb);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
rge_write_phy_ocp(sc, 0xb87c, 0x8fea);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
rge_write_phy_ocp(sc, 0xb87c, 0x80d6);
val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
rge_write_phy_ocp(sc, 0xb87e, val | 0xef00);
RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020);
RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
RGE_PHY_CLRBIT(sc, 0xa448, 0x0400);
RGE_PHY_CLRBIT(sc, 0xa586, 0x0400);
RGE_PHY_SETBIT(sc, 0xa430, 0x1001);
RGE_PHY_SETBIT(sc, 0xa442, 0x0080);
}
static void
rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever) rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever)
{ {
if (sc->rge_rcodever != rcodever) { if (sc->rge_rcodever != rcodever) {
int i; int i;
rge_patch_phy_mcu(sc, 1); rge_patch_phy_mcu(sc, 1);
if (sc->rge_type == MAC_R25) { if (sc->rge_type == MAC_R25) {
Show All 14 Lines if (sc->rge_type == MAC_R25) {
rge_write_phy_ocp(sc, 0xa438, 0); rge_write_phy_ocp(sc, 0xa438, 0);
RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
rge_write_phy_ocp(sc, 0xa436, 0x8024); rge_write_phy_ocp(sc, 0xa436, 0x8024);
rge_write_phy_ocp(sc, 0xa438, 0); rge_write_phy_ocp(sc, 0xa438, 0);
} else if (sc->rge_type == MAC_R25B) { } else if (sc->rge_type == MAC_R25B) {
for (i = 0; i < nitems(mac_r25b_mcu); i++) for (i = 0; i < nitems(mac_r25b_mcu); i++)
rge_write_phy_ocp(sc, rge_write_phy_ocp(sc,
mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val); mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);
} else if (sc->rge_type == MAC_R25D) { } else if (sc->rge_type == MAC_R25D_1) {
for (i = 0; i < 2403; i++) for (i = 0; i < 2403; i++)
rge_write_phy_ocp(sc, rge_write_phy_ocp(sc,
mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val); mac_r25d_1_mcu[i].reg,
mac_r25d_1_mcu[i].val);
rge_patch_phy_mcu(sc, 0); rge_patch_phy_mcu(sc, 0);
rge_patch_phy_mcu(sc, 1); rge_patch_phy_mcu(sc, 1);
for (; i < 2528; i++) for (; i < 2528; i++)
rge_write_phy_ocp(sc, rge_write_phy_ocp(sc,
mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val); mac_r25d_1_mcu[i].reg,
mac_r25d_1_mcu[i].val);
rge_patch_phy_mcu(sc, 0); rge_patch_phy_mcu(sc, 0);
rge_patch_phy_mcu(sc, 1); rge_patch_phy_mcu(sc, 1);
for (; i < nitems(mac_r25d_mcu); i++) for (; i < nitems(mac_r25d_1_mcu); i++)
rge_write_phy_ocp(sc, rge_write_phy_ocp(sc,
mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val); mac_r25d_1_mcu[i].reg,
mac_r25d_1_mcu[i].val);
} else if (sc->rge_type == MAC_R25D_2) {
for (i = 0; i < 1269; i++)
rge_write_phy_ocp(sc,
mac_r25d_2_mcu[i].reg,
mac_r25d_2_mcu[i].val);
rge_patch_phy_mcu(sc, 0);
rge_patch_phy_mcu(sc, 1);
for (; i < nitems(mac_r25d_2_mcu); i++)
rge_write_phy_ocp(sc,
mac_r25d_2_mcu[i].reg,
mac_r25d_2_mcu[i].val);
} else if (sc->rge_type == MAC_R26_1) { } else if (sc->rge_type == MAC_R26_1) {
for (i = 0; i < 6989; i++) for (i = 0; i < 6989; i++)
rge_write_phy_ocp(sc, rge_write_phy_ocp(sc,
mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val); mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
rge_patch_phy_mcu(sc, 0); rge_patch_phy_mcu(sc, 0);
rge_patch_phy_mcu(sc, 1); rge_patch_phy_mcu(sc, 1);
for (; i < nitems(mac_r26_1_mcu); i++) for (; i < nitems(mac_r26_1_mcu); i++)
▲ Show 20 Lines • Show All 524 Lines • Show Last 20 Lines