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Differential D55010 Diff 170845 sys/x86/cpufreq/hwpstate_amd.c

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sys/x86/cpufreq/hwpstate_amd.c

Show First 20 Lines • Show All 423 Lines • ▼ Show 20 Lines if (hwpstate_pkg_ctrl_enable) {
set_cppc_request_send_one(&data, hwp_dev); set_cppc_request_send_one(&data, hwp_dev);
error = data.res != 0 ? EFAULT : 0; error = data.res != 0 ? EFAULT : 0;
} }
return (error); return (error);
} }
static int static int
sysctl_epp_handler(SYSCTL_HANDLER_ARGS) sysctl_cppc_request_field_handler(SYSCTL_HANDLER_ARGS)
{ {
const u_int max_epp = const u_int max = BITS_VALUE(arg2, (uint64_t)-1);
BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, (uint64_t)-1);
const device_t dev = arg1; const device_t dev = arg1;
struct hwpstate_softc *const sc = device_get_softc(dev); struct hwpstate_softc *const sc = device_get_softc(dev);
u_int val; u_int val;
int error; int error;
/* Sysctl knob does not exist if PSTATE_CPPC is not set. */ /* Sysctl knob does not exist if PSTATE_CPPC is not set. */
check_cppc_enabled(sc, __func__); check_cppc_enabled(sc, __func__);
val = BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, sc->cppc.request); val = BITS_VALUE(arg2, sc->cppc.request);
error = sysctl_handle_int(oidp, &val, 0, req); error = sysctl_handle_int(oidp, &val, 0, req);
if (error != 0 || req->newptr == NULL) if (error != 0 || req->newptr == NULL)
return (error); return (error);
if (val > max_epp) if (val > max)
return (EINVAL); return (EINVAL);
error = set_cppc_request(dev, error = set_cppc_request(dev, BITS_WITH_VALUE(arg2, val),
BITS_WITH_VALUE(AMD_CPPC_REQUEST_EPP_BITS, val), BITS_WITH_VALUE(arg2, -1));
BITS_WITH_VALUE(AMD_CPPC_REQUEST_EPP_BITS, -1));
return (error); return (error);
} }
static driver_t hwpstate_driver = { static driver_t hwpstate_driver = {
HWP_AMD_CLASSNAME, HWP_AMD_CLASSNAME,
hwpstate_methods, hwpstate_methods,
sizeof(struct hwpstate_softc), sizeof(struct hwpstate_softc),
}; };
▲ Show 20 Lines • Show All 453 Lines • ▼ Show 20 Lines if ((sc->flags & PSTATE_CPPC) != 0) {
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_STATIC_CHILDREN(_debug), OID_AUTO, SYSCTL_STATIC_CHILDREN(_debug), OID_AUTO,
device_get_nameunit(dev), device_get_nameunit(dev),
CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE,
sc, 0, sysctl_cppc_dump_handler, "A", ""); sc, 0, sysctl_cppc_dump_handler, "A", "");
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
"epp", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, dev, 0, "epp", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
sysctl_epp_handler, "IU", dev, AMD_CPPC_REQUEST_EPP_BITS,
sysctl_cppc_request_field_handler, "IU",
"Efficiency/Performance Preference " "Efficiency/Performance Preference "
"(range from 0, most performant, through 255, most efficient)"); "(range from 0, most performant, through 255, most efficient)");
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
"min_perf", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
dev, AMD_CPPC_REQUEST_MIN_PERF_BITS,
sysctl_cppc_request_field_handler, "IU",
"Minimum allowed performance level (from 0 to 255, "
"must be smaller than 'max_perf', "
"effective range limited by CPU capabilities)");
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
"max_perf", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
dev, AMD_CPPC_REQUEST_MAX_PERF_BITS,
sysctl_cppc_request_field_handler, "IU",
"Maximum allowed performance level (from 0 to 255, "
"must be greater than 'min_perf', "
"effective range limited by CPU capabilities)");
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
"desired_perf", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
dev, AMD_CPPC_REQUEST_DES_PERF_BITS,
sysctl_cppc_request_field_handler, "IU",
"Desired performance (from 0 to 255, "
"0 means autonomous mode enabled, "
"otherwise value must be between 'min_perf' "
"and 'max_perf' inclusive)");
} }
return (cpufreq_register(dev)); return (cpufreq_register(dev));
} }
static int static int
hwpstate_get_info_from_msr(device_t dev) hwpstate_get_info_from_msr(device_t dev)
{ {
struct hwpstate_softc *sc; struct hwpstate_softc *sc;
▲ Show 20 Lines • Show All 160 Lines • Show Last 20 Lines