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sys/amd64/amd64/machdep.c
| Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Lines | |||||
| static void | static void | ||||
| late_ifunc_resolve(void *dummy __unused) | late_ifunc_resolve(void *dummy __unused) | ||||
| { | { | ||||
| link_elf_late_ireloc(); | link_elf_late_ireloc(); | ||||
| } | } | ||||
| SYSINIT(late_ifunc_resolve, SI_SUB_CPU, SI_ORDER_ANY, late_ifunc_resolve, NULL); | SYSINIT(late_ifunc_resolve, SI_SUB_CPU, SI_ORDER_ANY, late_ifunc_resolve, NULL); | ||||
| void | void | ||||
| cpu_setregs(void) | cpu_setregs(void) | ||||
| { | { | ||||
| register_t cr0; | register_t cr0; | ||||
| TSENTER(); | TSENTER(); | ||||
| cr0 = rcr0(); | cr0 = rcr0(); | ||||
| cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; | cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; | ||||
| ▲ Show 20 Lines • Show All 1,013 Lines • ▼ Show 20 Lines | hammer_time(u_int64_t modulep, u_int64_t physfree) | ||||
| TUNABLE_INT_FETCH("vm.pmap.pcid_invlpg_workaround", | TUNABLE_INT_FETCH("vm.pmap.pcid_invlpg_workaround", | ||||
| &pmap_pcid_invlpg_workaround_uena); | &pmap_pcid_invlpg_workaround_uena); | ||||
| cpu_init_small_core(); | cpu_init_small_core(); | ||||
| if ((cpu_feature2 & CPUID2_XSAVE) != 0) { | if ((cpu_feature2 & CPUID2_XSAVE) != 0) { | ||||
| use_xsave = 1; | use_xsave = 1; | ||||
| TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); | TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); | ||||
| } | } | ||||
| sched_instance_select(); | |||||
| link_elf_ireloc(); | link_elf_ireloc(); | ||||
| /* | /* | ||||
| * This may be done better later if it gets more high level | * This may be done better later if it gets more high level | ||||
| * components in it. If so just link td->td_proc here. | * components in it. If so just link td->td_proc here. | ||||
| */ | */ | ||||
| proc_linkup0(&proc0, &thread0); | proc_linkup0(&proc0, &thread0); | ||||
| ▲ Show 20 Lines • Show All 588 Lines • Show Last 20 Lines | |||||