Differential D54504 Diff 169250 usr.sbin/bhyve/aarch64/bhyverun_machdep.c

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usr.sbin/bhyve/aarch64/bhyverun_machdep.c

Show First 20 Lines • Show All 264 Lines • ▼ Show 20 Lines	mmio_uart_mem_handler(struct vcpu *vcpu __unused, int dir,
if (dir == MEM_F_WRITE)		if (dir == MEM_F_WRITE)
uart_pl011_write(sc, reg, *val);		uart_pl011_write(sc, reg, *val);
else		else
*val = uart_pl011_read(sc, reg);		*val = uart_pl011_read(sc, reg);

return (0);		return (0);
}		}

static bool		static int
init_mmio_uart(struct vmctx *ctx)		init_mmio_uart(struct vmctx *ctx)
{		{
struct uart_pl011_softc *sc;		struct uart_pl011_softc *sc;
struct mem_range mr;		struct mem_range mr;
const char *path;		const char *path;
int error;		int error;

path = get_config_value("console");		path = get_config_value("console");
if (path == NULL)		if (path == NULL)
return (false);		return (1);

sc = uart_pl011_init(mmio_uart_intr_assert, mmio_uart_intr_deassert,		sc = uart_pl011_init(mmio_uart_intr_assert, mmio_uart_intr_deassert,
ctx);		ctx);
if (uart_pl011_tty_open(sc, path) != 0) {		if (uart_pl011_tty_open(sc, path) != 0) {
EPRINTLN("Unable to initialize backend '%s' for mmio uart",		EPRINTLN("Unable to initialize backend '%s' for mmio uart",
path);		path);
assert(0);		return (-1);
}		}

bzero(&mr, sizeof(struct mem_range));		bzero(&mr, sizeof(struct mem_range));
mr.name = "uart";		mr.name = "uart";
mr.base = UART_MMIO_BASE;		mr.base = UART_MMIO_BASE;
mr.size = UART_MMIO_SIZE;		mr.size = UART_MMIO_SIZE;
mr.flags = MEM_F_RW;		mr.flags = MEM_F_RW;
mr.handler = mmio_uart_mem_handler;		mr.handler = mmio_uart_mem_handler;
mr.arg1 = sc;		mr.arg1 = sc;
mr.arg2 = mr.base;		mr.arg2 = mr.base;
error = register_mem(&mr);		error = register_mem(&mr);
assert(error == 0);		assert(error == 0);

return (true);		return (0);
}		}

static void		static void
mmio_rtc_intr_assert(void *arg)		mmio_rtc_intr_assert(void *arg)
{		{
struct vmctx *ctx = arg;		struct vmctx *ctx = arg;

vm_assert_irq(ctx, RTC_INTR);		vm_assert_irq(ctx, RTC_INTR);
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines	fdt_add_gic(GIC_DIST_BASE, GIC_DIST_SIZE, GIC_REDIST_BASE,
GIC_REDIST_SIZE(guest_ncpus));		GIC_REDIST_SIZE(guest_ncpus));
error = vm_attach_vgic(ctx, GIC_DIST_BASE, GIC_DIST_SIZE,		error = vm_attach_vgic(ctx, GIC_DIST_BASE, GIC_DIST_SIZE,
GIC_REDIST_BASE, GIC_REDIST_SIZE(guest_ncpus));		GIC_REDIST_BASE, GIC_REDIST_SIZE(guest_ncpus));
if (error != 0) {		if (error != 0) {
warn("vm_attach_vgic()");		warn("vm_attach_vgic()");
return (error);		return (error);
}		}

if (init_mmio_uart(ctx))		error = init_mmio_uart(ctx);
		if (error == 0)
fdt_add_uart(UART_MMIO_BASE, UART_MMIO_SIZE, UART_INTR);		fdt_add_uart(UART_MMIO_BASE, UART_MMIO_SIZE, UART_INTR);
		else if (error < 0)
		return (error);
init_mmio_rtc(ctx);		init_mmio_rtc(ctx);
fdt_add_rtc(RTC_MMIO_BASE, RTC_MMIO_SIZE, RTC_INTR);		fdt_add_rtc(RTC_MMIO_BASE, RTC_MMIO_SIZE, RTC_INTR);
fdt_add_timer();		fdt_add_timer();
pci_irq_init(pcie_intrs);		pci_irq_init(pcie_intrs);
fdt_add_pcie(pcie_intrs);		fdt_add_pcie(pcie_intrs);

/* Mark CPU0 as running */		/* Mark CPU0 as running */
CPU_SET(0, &running_cpumask);		CPU_SET(0, &running_cpumask);
Show All 16 Lines