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Differential D6250 Diff 17314 head/sys/dev/bhnd/cores/chipc/chipc.c

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head/sys/dev/bhnd/cores/chipc/chipc.c

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/* /*
* Broadcom ChipCommon driver. * Broadcom ChipCommon driver.
* *
* With the exception of some very early chipsets, the ChipCommon core * With the exception of some very early chipsets, the ChipCommon core
* has been included in all HND SoCs and chipsets based on the siba(4) * has been included in all HND SoCs and chipsets based on the siba(4)
* and bcma(4) interconnects, providing a common interface to chipset * and bcma(4) interconnects, providing a common interface to chipset
* identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO,
* flash, etc. * flash, etc.
*
* The purpose of this driver is memory resource management for ChipCommon drivers
* like UART, PMU, flash. ChipCommon core has several memory regions.
*
* ChipCommon driver has memory resource manager. Driver
* gets information about BHND core ports/regions and map them
* into drivers' resources.
*
* Here is overview of mapping:
*
* ------------------------------------------------------
* | Port.Region| Purpose |
* ------------------------------------------------------
* | 0.0 | PMU, SPI(0x40), UART(0x300) |
* | 1.0 | ? |
* | 1.1 | MMIO flash (SPI & CFI) |
* ------------------------------------------------------
*/ */
#include <sys/param.h> #include <sys/param.h>
#include <sys/kernel.h> #include <sys/kernel.h>
#include <sys/lock.h> #include <sys/lock.h>
#include <sys/bus.h> #include <sys/bus.h>
#include <sys/rman.h>
#include <sys/malloc.h> #include <sys/malloc.h>
#include <sys/module.h> #include <sys/module.h>
#include <sys/mutex.h> #include <sys/mutex.h>
#include <sys/systm.h> #include <sys/systm.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h> #include <machine/resource.h>
#include <dev/bhnd/bhnd.h> #include <dev/bhnd/bhnd.h>
#include <dev/bhnd/bhndvar.h> #include <dev/bhnd/bhndvar.h>
#include "chipcreg.h" #include "chipcreg.h"
#include "chipcvar.h" #include "chipcvar.h"
#include "chipc_private.h" #include "chipc_private.h"
Show All 31 Linesstatic struct bhnd_device_quirk chipc_quirks[] = {
BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
BHND_DEVICE_QUIRK_END BHND_DEVICE_QUIRK_END
}; };
/*
* Here is resource configuration hints for child devices
*
* [Flash] There are 2 flash resources:
* - resource ID (rid) = 0: memory-mapped flash memory
* - resource ID (rid) = 1: memory-mapped flash registers (i.e for SPI)
*
* [UART] Uses IRQ and memory resources:
* - resource ID (rid) = 0: memory-mapped registers
* - IRQ resource ID (rid) = 0: shared IRQ line for Tx/Rx.
*/
static const struct chipc_hint { static const struct chipc_hint {
const char *name; const char *name;
int unit; int unit;
int type; int type;
int rid; int rid;
rman_res_t base; /* relative to parent resource */ rman_res_t base; /* relative to parent resource */
rman_res_t size; rman_res_t size;
u_int port; /* ignored if SYS_RES_IRQ */ u_int port; /* ignored if SYS_RES_IRQ */
▲ Show 20 Lines • Show All 1,173 Lines • ▼ Show 20 Lines
chipc_get_caps(device_t dev) chipc_get_caps(device_t dev)
{ {
struct chipc_softc *sc; struct chipc_softc *sc;
sc = device_get_softc(dev); sc = device_get_softc(dev);
return (&sc->caps); return (&sc->caps);
} }
static uint32_t
chipc_get_flash_cfg(device_t dev)
{
struct chipc_softc *sc;
sc = device_get_softc(dev);
return (bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG));
}
static device_method_t chipc_methods[] = { static device_method_t chipc_methods[] = {
/* Device interface */ /* Device interface */
DEVMETHOD(device_probe, chipc_probe), DEVMETHOD(device_probe, chipc_probe),
DEVMETHOD(device_attach, chipc_attach), DEVMETHOD(device_attach, chipc_attach),
DEVMETHOD(device_detach, chipc_detach), DEVMETHOD(device_detach, chipc_detach),
DEVMETHOD(device_suspend, chipc_suspend), DEVMETHOD(device_suspend, chipc_suspend),
DEVMETHOD(device_resume, chipc_resume), DEVMETHOD(device_resume, chipc_resume),
Show All 26 Linesstatic device_method_t chipc_methods[] = {
DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
/* ChipCommon interface */ /* ChipCommon interface */
DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src),
DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins),
DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins),
DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
DEVMETHOD(bhnd_chipc_get_flash_cfg, chipc_get_flash_cfg),
DEVMETHOD_END DEVMETHOD_END
}; };
DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc));
DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0); EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0,
BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
MODULE_VERSION(bhnd_chipc, 1); MODULE_VERSION(bhnd_chipc, 1);