Differential D6220 Diff 17237 head/sys/boot/fdt/dts/arm/armada-38x.dtsi

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head/sys/boot/fdt/dts/arm/armada-38x.dtsi

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	/ {
model = "Marvell Armada 38x family SoC";		model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada380";		compatible = "marvell,armada380";

aliases {		aliases {
gpio0 = &gpio0;		gpio0 = &gpio0;
gpio1 = &gpio1;		gpio1 = &gpio1;
serial0 = &uart0;		serial0 = &uart0;
serial1 = &uart1;		serial1 = &uart1;
		sram0 = &SRAM0;
		sram1 = &SRAM1;
};		};

pmu {		pmu {
compatible = "arm,cortex-a9-pmu";		compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;		interrupts-extended = <&mpic 3>;
};		};

		SRAM0: sram@f1100000 {
		compatible = "mrvl,cesa-sram";
		reg = <0xf1100000 0x0010000>;
		};

		SRAM1: sram@f1110000 {
		compatible = "mrvl,cesa-sram";
		reg = <0xf1110000 0x0010000>;
		};

soc {		soc {
compatible = "marvell,armada380-mbus", "simple-bus";		compatible = "marvell,armada380-mbus", "simple-bus";
#address-cells = <2>;		#address-cells = <2>;
#size-cells = <1>;		#size-cells = <1>;
controller = <&mbusc>;		controller = <&mbusc>;
interrupt-parent = <&gic>;		interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;		pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;		pcie-io-aperture = <0xe8000000 0x100000>;
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	devbus-cs3 {
status = "disabled";		status = "disabled";
};		};

internal-regs {		internal-regs {
compatible = "simple-bus";		compatible = "simple-bus";
#address-cells = <1>;		#address-cells = <1>;
#size-cells = <1>;		#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;		ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

		crypto@90000 {
		compatible = "mrvl,cesa";
		reg = <0x90000 0x10000>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		sram-handle = <&SRAM0>;
		status = "disabled";
		};

		crypto@92000 {
		compatible = "mrvl,cesa";
		reg = <0x92000 0x1000 /* tdma base reg chan 1 */
		0x9F000 0x1000>; /* cesa base reg chan 1 */
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		sram-handle = <&SRAM1>;
		status = "disabled";
		};

L2: cache-controller@8000 {		L2: cache-controller@8000 {
compatible = "arm,pl310-cache";		compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;		reg = <0x8000 0x1000>;
cache-unified;		cache-unified;
cache-level = <2>;		cache-level = <2>;
};		};

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