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sys/dev/qcom_gcc/qcom_gcc_ipq4018_clock.c
| Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines | F_BRANCH2(GCC_SDCC1_APPS_CLK, "gcc_sdcc1_apps_clk", | ||||
| false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| F_BRANCH2(GCC_TLMM_AHB_CLK, "gcc_tlmm_ahb_clk", "pcnoc_clk_src", | F_BRANCH2(GCC_TLMM_AHB_CLK, "gcc_tlmm_ahb_clk", "pcnoc_clk_src", | ||||
| 0x6000, 5, 0, 0, 0x5004, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x6000, 5, 0, 0, 0x5004, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| true, 0), /* BRANCH_HALT_VOTED */ | true, 0), /* BRANCH_HALT_VOTED */ | ||||
| F_BRANCH2(GCC_USB2_MASTER_CLK, "gcc_usb2_master_clk", "pcnoc_clk_src", | F_BRANCH2(GCC_USB2_MASTER_CLK, "gcc_usb2_master_clk", "pcnoc_clk_src", | ||||
| 0x1e00c, 0, 0, 0, 0x1e00c, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1e00c, 0, 0, 0, 0x1e00c, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| F_BRANCH2(GCC_USB2_SLEEP_CLK, "gcc_usb2_sleep_clk", | F_BRANCH2(GCC_USB2_SLEEP_CLK, "gcc_usb2_sleep_clk", | ||||
| "gcc_sleep_clk_src", 0x1e010, 0, 0, 0, 0x1e010, | "sleep_clk", 0x1e010, 0, 0, 0, 0x1e010, | ||||
| QCOM_CLK_BRANCH2_BRANCH_HALT, | QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| F_BRANCH2(GCC_USB2_MOCK_UTMI_CLK, "gcc_usb2_mock_utmi_clk", | F_BRANCH2(GCC_USB2_MOCK_UTMI_CLK, "gcc_usb2_mock_utmi_clk", | ||||
| "usb30_mock_utmi_clk_src", 0x1e014, 0, 0, 0, 0x1e014, | "usb30_mock_utmi_clk_src", 0x1e014, 0, 0, 0, 0x1e014, | ||||
| QCOM_CLK_BRANCH2_BRANCH_HALT, | QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| F_BRANCH2(GCC_USB3_MASTER_CLK, "gcc_usb3_master_clk", "fepll125", | F_BRANCH2(GCC_USB3_MASTER_CLK, "gcc_usb3_master_clk", "fepll125", | ||||
| 0x1e028, 0, 0, 0, 0x1e028, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1e028, 0, 0, 0, 0x1e028, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| F_BRANCH2(GCC_USB3_SLEEP_CLK, "gcc_usb3_sleep_clk", "gcc_sleep_clk_src", | F_BRANCH2(GCC_USB3_SLEEP_CLK, "gcc_usb3_sleep_clk", "sleep_clk", | ||||
| 0x1e02c, 0, 0, 0, 0x1e02c, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1e02c, 0, 0, 0, 0x1e02c, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| F_BRANCH2(GCC_USB3_MOCK_UTMI_CLK, "gcc_usb3_mock_utmi_clk", | F_BRANCH2(GCC_USB3_MOCK_UTMI_CLK, "gcc_usb3_mock_utmi_clk", | ||||
| "usb30_mock_utmi_clk_src", | "usb30_mock_utmi_clk_src", | ||||
| 0x1e030, 0, 0, 0, 0x1e030, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1e030, 0, 0, 0, 0x1e030, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| /* Note - yes, these two have the same registers in linux */ | /* Note - yes, these two have the same registers in linux */ | ||||
| F_BRANCH2(GCC_WCSS2G_CLK, "gcc_wcss2g_clk", "wcss2g_clk_src", | F_BRANCH2(GCC_WCSS2G_CLK, "gcc_wcss2g_clk", "wcss2g_clk_src", | ||||
| 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| F_BRANCH2(GCC_WCSS2G_REF_CLK, "gcc_wcss2g_ref_clk", "xo", | F_BRANCH2(GCC_WCSS2G_REF_CLK, "gcc_wcss2g_ref_clk", "xo", | ||||
| 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1f00c, 0, 0, 0, 0x1f00c, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| F_BRANCH2(GCC_WCSS2G_RTC_CLK, "gcc_wcss2g_rtc_clk", "gcc_sleep_clk_src", | /* | ||||
| * TODO: figure out whether gcc_sleep_clk_src -> sleep_clk is right; | |||||
adrian: i did; they don't have a separate node for the sleep clock, but they do for the other chipsets. | |||||
| * will need to go consult the openwrt ipq4018 device tree / code | |||||
| * again! | |||||
| */ | |||||
| F_BRANCH2(GCC_WCSS2G_RTC_CLK, "gcc_wcss2g_rtc_clk", "sleep_clk", | |||||
| 0x1f010, 0, 0, 0, 0x1f010, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1f010, 0, 0, 0, 0x1f010, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| /* Note - yes, these two have the same registers in linux */ | /* Note - yes, these two have the same registers in linux */ | ||||
| F_BRANCH2(GCC_WCSS5G_CLK, "gcc_wcss5g_clk", "wcss5g_clk_src", | F_BRANCH2(GCC_WCSS5G_CLK, "gcc_wcss5g_clk", "wcss5g_clk_src", | ||||
| 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| F_BRANCH2(GCC_WCSS5G_REF_CLK, "gcc_wcss5g_ref_clk", "xo", | F_BRANCH2(GCC_WCSS5G_REF_CLK, "gcc_wcss5g_ref_clk", "xo", | ||||
| 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1f00c, 0, 0, 0, 0x2000c, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | false, QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| F_BRANCH2(GCC_WCSS5G_RTC_CLK, "gcc_wcss5g_rtc_clk", "gcc_sleep_clk_src", | F_BRANCH2(GCC_WCSS5G_RTC_CLK, "gcc_wcss5g_rtc_clk", "sleep_clk", | ||||
| 0x1f010, 0, 0, 0, 0x20010, QCOM_CLK_BRANCH2_BRANCH_HALT, | 0x1f010, 0, 0, 0, 0x20010, QCOM_CLK_BRANCH2_BRANCH_HALT, | ||||
| false, 0), | false, 0), | ||||
| F_BRANCH2(GCC_PCNOC_AHB_CLK, "pcnoc_clk_src", "gcc_pcnoc_ahb_clk_src", | F_BRANCH2(GCC_PCNOC_AHB_CLK, "pcnoc_clk_src", "gcc_pcnoc_ahb_clk_src", | ||||
| 0x21030, 0, 0, 0, 0x21030, QCOM_CLK_BRANCH2_BRANCH_HALT, false, | 0x21030, 0, 0, 0, 0x21030, QCOM_CLK_BRANCH2_BRANCH_HALT, false, | ||||
| QCOM_CLK_BRANCH2_FLAGS_CRITICAL | | QCOM_CLK_BRANCH2_FLAGS_CRITICAL | | ||||
| QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT), | ||||
| }; | }; | ||||
| ▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines | |||||
i did; they don't have a separate node for the sleep clock, but they do for the other chipsets.