Differential D46723 Diff 143550 sys/arm/ti/clk/ti_dpll_clock.c

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sys/arm/ti/clk/ti_dpll_clock.c

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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;		* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED		* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,		* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY		* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF		* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.		* SUCH DAMAGE.
*/		*/

		/*
		* Devicetree description
		* Documentation/devicetree/bindings/clock/ti/dpll.txt
		*/

#include <sys/param.h>		#include <sys/param.h>
#include <sys/conf.h>		#include <sys/conf.h>
#include <sys/bus.h>		#include <sys/bus.h>
#include <sys/kernel.h>		#include <sys/kernel.h>
#include <sys/module.h>		#include <sys/module.h>
#include <sys/systm.h>		#include <sys/systm.h>
#include <sys/libkern.h>		#include <sys/libkern.h>

#include <machine/bus.h>		#include <machine/bus.h>
#include <dev/fdt/simplebus.h>		#include <dev/fdt/simplebus.h>

#include <dev/clk/clk_div.h>		#include <dev/clk/clk_div.h>
#include <dev/ofw/ofw_bus.h>		#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>		#include <dev/ofw/ofw_bus_subr.h>

		#include <arm/ti/clk/am33xx.h>
#include <arm/ti/clk/ti_clk_dpll.h>		#include <arm/ti/clk/ti_clk_dpll.h>
#include "clock_common.h"		#include <arm/ti/clk/ti_clock_common.h>

#if 0		#if 0
#define DPRINTF(dev, msg...) device_printf(dev, msg)		#define DPRINTF(dev, msg...) device_printf(dev, msg)
#else		#else
#define DPRINTF(dev, msg...)		#define DPRINTF(dev, msg...)
#endif		#endif

/*
* Devicetree description
* Documentation/devicetree/bindings/clock/ti/dpll.txt
*/

struct ti_dpll_softc {		struct ti_dpll_softc {
device_t dev;		device_t dev;
uint8_t dpll_type;		uint8_t dpll_type;

bool attach_done;
struct ti_clk_dpll_def dpll_def;		struct ti_clk_dpll_def dpll_def;

struct clock_cell_info clock_cell;
struct clkdom *clkdom;		struct clkdom *clkdom;
};		};

static int ti_dpll_probe(device_t dev);		static int ti_dpll_probe(device_t dev);
static int ti_dpll_attach(device_t dev);		static int ti_dpll_attach(device_t dev);
static int ti_dpll_detach(device_t dev);		static int ti_dpll_detach(device_t dev);

#define TI_OMAP3_DPLL_CLOCK 17		#define TI_OMAP3_DPLL_CLOCK 17
Show All 32 Lines	static struct ofw_compat_data compat_data[] = {
{ "ti,am3-dpll-clock", TI_AM3_DPLL_CLOCK },		{ "ti,am3-dpll-clock", TI_AM3_DPLL_CLOCK },
{ "ti,am3-dpll-core-clock", TI_AM3_DPLL_CORE_CLOCK },		{ "ti,am3-dpll-core-clock", TI_AM3_DPLL_CORE_CLOCK },
{ "ti,am3-dpll-x2-clock", TI_AM3_DPLL_X2_CLOCK },		{ "ti,am3-dpll-x2-clock", TI_AM3_DPLL_X2_CLOCK },
{ "ti,omap2-dpll-core-clock", TI_OMAP2_DPLL_CORE_CLOCK },		{ "ti,omap2-dpll-core-clock", TI_OMAP2_DPLL_CORE_CLOCK },
{ NULL, TI_DPLL_END }		{ NULL, TI_DPLL_END }
};		};

static int		static int
register_clk(struct ti_dpll_softc *sc) {
int err;

sc->clkdom = clkdom_create(sc->dev);
if (sc->clkdom == NULL) {
DPRINTF(sc->dev, "Failed to create clkdom\n");
return (ENXIO);
}

err = ti_clknode_dpll_register(sc->clkdom, &sc->dpll_def);
if (err) {
DPRINTF(sc->dev,
"ti_clknode_dpll_register failed %x\n", err);
return (ENXIO);
}

err = clkdom_finit(sc->clkdom);
if (err) {
DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err);
return (ENXIO);
}

return (0);
}

static int
ti_dpll_probe(device_t dev)		ti_dpll_probe(device_t dev)
{		{
if (!ofw_bus_status_okay(dev))		if (!ofw_bus_status_okay(dev))
return (ENXIO);		return (ENXIO);

if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)		if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);		return (ENXIO);

device_set_desc(dev, "TI DPLL Clock");		device_set_desc(dev, "TI DPLL Clock");
		if (bootverbose == 0)
		device_quiet(dev);

return (BUS_PROBE_DEFAULT);		return (BUS_PROBE_DEFAULT);
}		}

static int		static int
parse_dpll_reg(struct ti_dpll_softc *sc) {		parse_dpll_reg(struct ti_dpll_softc *sc) {
ssize_t numbytes_regs;		ssize_t numbytes_regs;
uint32_t num_regs;		uint32_t num_regs;
phandle_t node;		phandle_t node;
cell_t reg_cells[4];		cell_t reg_cells[6];

if (sc->dpll_type == TI_AM3_DPLL_X2_CLOCK \|\|		if (sc->dpll_type == TI_AM3_DPLL_X2_CLOCK \|\|
sc->dpll_type == TI_OMAP4_DPLL_X2_CLOCK) {		sc->dpll_type == TI_OMAP4_DPLL_X2_CLOCK) {
sc->dpll_def.ti_clksel_mult.value = 2;		sc->dpll_def.ti_clksel_mult.value = 2;
sc->dpll_def.ti_clksel_mult.flags = TI_CLK_FACTOR_FIXED;		sc->dpll_def.ti_clksel_mult.flags = TI_CLK_FACTOR_FIXED;

sc->dpll_def.ti_clksel_div.value = 1;		sc->dpll_def.ti_clksel_div.value = 1;
sc->dpll_def.ti_clksel_div.flags = TI_CLK_FACTOR_FIXED;		sc->dpll_def.ti_clksel_div.flags = TI_CLK_FACTOR_FIXED;
return (0);		return (0);
}		}

node = ofw_bus_get_node(sc->dev);		node = ofw_bus_get_node(sc->dev);

numbytes_regs = OF_getproplen(node, "reg");		numbytes_regs = OF_getproplen(node, "reg");
num_regs = numbytes_regs / sizeof(cell_t);		num_regs = numbytes_regs / sizeof(cell_t);

/* Sanity check */		/* Sanity check */
if (num_regs > 4)		if (num_regs > 6)
return (ENXIO);		return (ENXIO);

OF_getencprop(node, "reg", reg_cells, numbytes_regs);		OF_getencprop(node, "reg", reg_cells, numbytes_regs);

switch (sc->dpll_type) {		switch (sc->dpll_type) {
case TI_AM3_DPLL_NO_GATE_CLOCK:		case TI_AM3_DPLL_NO_GATE_CLOCK:
case TI_AM3_DPLL_J_TYPE_CLOCK:		case TI_AM3_DPLL_J_TYPE_CLOCK:
case TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK:		case TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK:
case TI_AM3_DPLL_CLOCK:		case TI_AM3_DPLL_CLOCK:
case TI_AM3_DPLL_CORE_CLOCK:		case TI_AM3_DPLL_CORE_CLOCK:
case TI_AM3_DPLL_X2_CLOCK:		case TI_AM3_DPLL_X2_CLOCK:
if (num_regs != 3)
return (ENXIO);
sc->dpll_def.ti_clkmode_offset = reg_cells[0];		sc->dpll_def.ti_clkmode_offset = reg_cells[0];
sc->dpll_def.ti_idlest_offset = reg_cells[1];		sc->dpll_def.ti_idlest_offset = reg_cells[1];
sc->dpll_def.ti_clksel_offset = reg_cells[2];		sc->dpll_def.ti_clksel_offset = reg_cells[2];
		/* Do not have autoidle */
		sc->dpll_def.ti_ssc_deltam_offset = reg_cells[3];
		sc->dpll_def.ti_ssc_modfreq_offset = reg_cells[4];
break;		break;

case TI_OMAP2_DPLL_CORE_CLOCK:		case TI_OMAP2_DPLL_CORE_CLOCK:
if (num_regs != 2)		if (num_regs != 2)
return (ENXIO);		return (ENXIO);
sc->dpll_def.ti_clkmode_offset = reg_cells[0];		sc->dpll_def.ti_clkmode_offset = reg_cells[0];
sc->dpll_def.ti_clksel_offset = reg_cells[1];		sc->dpll_def.ti_clksel_offset = reg_cells[1];
break;		break;

default:		default:
sc->dpll_def.ti_clkmode_offset = reg_cells[0];		sc->dpll_def.ti_clkmode_offset = reg_cells[0];
sc->dpll_def.ti_idlest_offset = reg_cells[1];		sc->dpll_def.ti_idlest_offset = reg_cells[1];
sc->dpll_def.ti_clksel_offset = reg_cells[2];		sc->dpll_def.ti_clksel_offset = reg_cells[2];
sc->dpll_def.ti_autoidle_offset = reg_cells[3];		sc->dpll_def.ti_autoidle_offset = reg_cells[3];
		sc->dpll_def.ti_ssc_deltam_offset = reg_cells[4];
		sc->dpll_def.ti_ssc_modfreq_offset = reg_cells[5];
break;		break;
}		}

/* AM335x */		/* AM335x */
if (sc->dpll_def.ti_clksel_offset == CM_CLKSEL_DPLL_PERIPH) {		if (sc->dpll_def.ti_clksel_offset == CM_CLKSEL_DPLL_PERIPH) {
sc->dpll_def.ti_clksel_mult.shift = 8;		sc->dpll_def.ti_clksel_mult.shift = 8;
sc->dpll_def.ti_clksel_mult.mask = 0x000FFF00;		sc->dpll_def.ti_clksel_mult.mask = 0x000FFF00;
sc->dpll_def.ti_clksel_mult.width = 12;		sc->dpll_def.ti_clksel_mult.width = 12;
Show All 37 Lines	DPRINTF(sc->dev, "clkmode %x idlest %x clksel %x autoidle %x\n",
sc->dpll_def.ti_clksel_offset,		sc->dpll_def.ti_clksel_offset,
sc->dpll_def.ti_autoidle_offset);		sc->dpll_def.ti_autoidle_offset);

return (0);		return (0);
}		}
static int		static int
ti_dpll_attach(device_t dev)		ti_dpll_attach(device_t dev)
{		{
struct ti_dpll_softc *sc;		struct ti_dpll_softc *sc;
phandle_t node;		phandle_t node;
int err;		int err, index;
		const char *node_name;

sc = device_get_softc(dev);		sc = device_get_softc(dev);
sc->dev = dev;		sc->dev = dev;

sc->dpll_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;		sc->dpll_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
node = ofw_bus_get_node(dev);		node = ofw_bus_get_node(dev);

		clk_parse_ofw_clk_name(dev, node, &node_name);
		if (node_name == NULL) {
		panic("Cannot get name of the clock node");
		}

/* Grab the content of reg properties */		/* Grab the content of reg properties */
parse_dpll_reg(sc);		parse_dpll_reg(sc);

/* default flags (OMAP4&AM335x) not present in the dts at moment */		/* default flags (OMAP4&AM335x) not present in the dts at moment */
sc->dpll_def.ti_clkmode_flags = MN_BYPASS_MODE_FLAG \| LOCK_MODE_FLAG;		sc->dpll_def.ti_clkmode_flags = MN_BYPASS_MODE_FLAG \| LOCK_MODE_FLAG;

if (OF_hasprop(node, "ti,low-power-stop")) {		if (OF_hasprop(node, "ti,low-power-stop")) {
sc->dpll_def.ti_clkmode_flags \|= LOW_POWER_STOP_MODE_FLAG;		sc->dpll_def.ti_clkmode_flags \|= LOW_POWER_STOP_MODE_FLAG;
}		}
if (OF_hasprop(node, "ti,low-power-bypass")) {		if (OF_hasprop(node, "ti,low-power-bypass")) {
sc->dpll_def.ti_clkmode_flags \|= IDLE_BYPASS_LOW_POWER_MODE_FLAG;		sc->dpll_def.ti_clkmode_flags \|= IDLE_BYPASS_LOW_POWER_MODE_FLAG;
}		}
if (OF_hasprop(node, "ti,lock")) {		if (OF_hasprop(node, "ti,lock")) {
sc->dpll_def.ti_clkmode_flags \|= LOCK_MODE_FLAG;		sc->dpll_def.ti_clkmode_flags \|= LOCK_MODE_FLAG;
}		}
		if (OF_hasprop(node, "ti,min-div")) {
		}
		if (OF_hasprop(node, "ti,ssc-deltam")) {
		}
		if (OF_hasprop(node, "ti,ssc-modfreq-hz")) {
		}
		if (OF_hasprop(node, "ti,ssc-downspread")) {
		}

read_clock_cells(sc->dev, &sc->clock_cell);		/* Find parent in lookup table */
		for (index = 0; index < nitems(dpll_parent_table); index++) {
		if (strcmp(node_name, dpll_parent_table[index].node_name) == 0)
		break;
		}

create_clkdef(sc->dev, &sc->clock_cell, &sc->dpll_def.clkdef);		if (index == nitems(dpll_parent_table))
		panic("Cant find clock %s\n", node_name);

err = find_parent_clock_names(sc->dev, &sc->clock_cell,		DPRINTF(sc->dev, "%s at dpll_parent_table[%d]\n", node_name, index);
&sc->dpll_def.clkdef);

if (err) {		/* Fill clknode_init_def */
/* free_clkdef will be called in ti_dpll_new_pass */		sc->dpll_def.clkdef.id = 1;
DPRINTF(sc->dev, "find_parent_clock_names failed\n");		sc->dpll_def.clkdef.name = dpll_parent_table[index].node_name;
return (bus_generic_attach(sc->dev));		sc->dpll_def.clkdef.parent_cnt = dpll_parent_table[index].parent_cnt;
		sc->dpll_def.clkdef.parent_names =
		dpll_parent_table[index].parent_names;
		sc->dpll_def.clkdef.flags = CLK_NODE_STATIC_STRINGS;

		sc->clkdom = clkdom_create(sc->dev);
		if (sc->clkdom == NULL) {
		DPRINTF(sc->dev, "Failed to create clkdom\n");
		return (ENXIO);
}		}

err = register_clk(sc);		err = ti_clknode_dpll_register(sc->clkdom, &sc->dpll_def);
		if (err != 0) {
		DPRINTF(sc->dev,
		"ti_clknode_dpll_register failed %x\n", err);
		return (ENXIO);
		}

if (err) {		err = clkdom_finit(sc->clkdom);
/* free_clkdef will be called in ti_dpll_new_pass */		if (err != 0) {
DPRINTF(sc->dev, "register_clk failed\n");		DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err);
return (bus_generic_attach(sc->dev));		return (ENXIO);
}		}

sc->attach_done = true;

free_clkdef(&sc->dpll_def.clkdef);

return (bus_generic_attach(sc->dev));		return (bus_generic_attach(sc->dev));
}		}

static int		static int
ti_dpll_detach(device_t dev)		ti_dpll_detach(device_t dev)
{		{
return (EBUSY);		return (EBUSY);
}		}

static void
ti_dpll_new_pass(device_t dev)
{
struct ti_dpll_softc *sc;
int err;

sc = device_get_softc(dev);

if (sc->attach_done) {
return;
}

err = find_parent_clock_names(sc->dev, &sc->clock_cell,
&sc->dpll_def.clkdef);
if (err) {
/* free_clkdef will be called in a later call to ti_dpll_new_pass */
DPRINTF(sc->dev,
"new_pass find_parent_clock_names failed\n");
return;
}

err = register_clk(sc);
if (err) {
/* free_clkdef will be called in a later call to ti_dpll_new_pass */
DPRINTF(sc->dev, "new_pass register_clk failed\n");
return;
}

sc->attach_done = true;
free_clkdef(&sc->dpll_def.clkdef);
}

static device_method_t ti_dpll_methods[] = {		static device_method_t ti_dpll_methods[] = {
/* Device interface */		/* Device interface */
DEVMETHOD(device_probe, ti_dpll_probe),		DEVMETHOD(device_probe, ti_dpll_probe),
DEVMETHOD(device_attach, ti_dpll_attach),		DEVMETHOD(device_attach, ti_dpll_attach),
DEVMETHOD(device_detach, ti_dpll_detach),		DEVMETHOD(device_detach, ti_dpll_detach),

/* Bus interface */
DEVMETHOD(bus_new_pass, ti_dpll_new_pass),

DEVMETHOD_END		DEVMETHOD_END
};		};

DEFINE_CLASS_0(ti_dpll, ti_dpll_driver, ti_dpll_methods,		DEFINE_CLASS_0(ti_dpll, ti_dpll_driver, ti_dpll_methods,
sizeof(struct ti_dpll_softc));		sizeof(struct ti_dpll_softc));

EARLY_DRIVER_MODULE(ti_dpll, simplebus, ti_dpll_driver, 0, 0,		EARLY_DRIVER_MODULE(ti_dpll, simplebus, ti_dpll_driver, 0, 0,
BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);		BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
MODULE_VERSION(ti_dpll, 1);		MODULE_VERSION(ti_dpll, 1);