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sys/dev/ixl/ixl.h
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#include <dev/pci/pcivar.h> | #include <dev/pci/pcivar.h> | ||||
#include <dev/pci/pcireg.h> | #include <dev/pci/pcireg.h> | ||||
#include <sys/proc.h> | #include <sys/proc.h> | ||||
#include <sys/sysctl.h> | #include <sys/sysctl.h> | ||||
#include <sys/endian.h> | #include <sys/endian.h> | ||||
#include <sys/taskqueue.h> | #include <sys/taskqueue.h> | ||||
#include <sys/pcpu.h> | #include <sys/pcpu.h> | ||||
#include <sys/smp.h> | #include <sys/smp.h> | ||||
#include <sys/sbuf.h> | |||||
#include <machine/smp.h> | #include <machine/smp.h> | ||||
#ifdef PCI_IOV | #ifdef PCI_IOV | ||||
#include <sys/nv.h> | #include <sys/nv.h> | ||||
#include <sys/iov_schema.h> | #include <sys/iov_schema.h> | ||||
#include <dev/pci/pci_iov.h> | #include <dev/pci/pci_iov.h> | ||||
#endif | #endif | ||||
#include "i40e_type.h" | #include "i40e_type.h" | ||||
#include "i40e_prototype.h" | #include "i40e_prototype.h" | ||||
#if defined(IXL_DEBUG) || defined(IXL_DEBUG_SYSCTL) | #if defined(IXL_DEBUG) || defined(IXL_DEBUG_SYSCTL) | ||||
#include <sys/sbuf.h> | |||||
#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x" | #define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x" | ||||
#define MAC_FORMAT_ARGS(mac_addr) \ | #define MAC_FORMAT_ARGS(mac_addr) \ | ||||
(mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \ | (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \ | ||||
(mac_addr)[4], (mac_addr)[5] | (mac_addr)[4], (mac_addr)[5] | ||||
#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off") | #define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off") | ||||
#endif /* IXL_DEBUG || IXL_DEBUG_SYSCTL */ | #endif /* IXL_DEBUG || IXL_DEBUG_SYSCTL */ | ||||
#ifdef IXL_DEBUG | #ifdef IXL_DEBUG | ||||
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#define HW_DEBUGOUT(...) | #define HW_DEBUGOUT(...) | ||||
#endif /* IXL_DEBUG */ | #endif /* IXL_DEBUG */ | ||||
/* Tunables */ | /* Tunables */ | ||||
/* | /* | ||||
* Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the | * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the | ||||
* number of tx/rx descriptors allocated by the driver. Increasing this | * number of tx/rx descriptors allocated by the driver. Increasing this | ||||
* value allows the driver to queue more operations. Each descriptor is 16 | * value allows the driver to queue more operations. | ||||
* or 32 bytes (configurable in FVL) | * | ||||
* Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes. | |||||
* The driver currently always uses 32 byte Rx descriptors. | |||||
*/ | */ | ||||
#define DEFAULT_RING 1024 | #define DEFAULT_RING 1024 | ||||
#define PERFORM_RING 2048 | #define PERFORM_RING 2048 | ||||
#define MAX_RING 4096 | #define MAX_RING 4096 | ||||
#define MIN_RING 32 | #define MIN_RING 32 | ||||
/* | /* | ||||
** Default number of entries in Tx queue buf_ring. | ** Default number of entries in Tx queue buf_ring. | ||||
*/ | */ | ||||
#define SMALL_TXBRSZ 4096 | #define SMALL_TXBRSZ 4096 | ||||
/* This may require mbuf cluster tuning */ | /* This may require mbuf cluster tuning */ | ||||
#define DEFAULT_TXBRSZ (SMALL_TXBRSZ * SMALL_TXBRSZ) | #define DEFAULT_TXBRSZ (SMALL_TXBRSZ * SMALL_TXBRSZ) | ||||
/* Alignment for rings */ | /* Alignment for rings */ | ||||
#define DBA_ALIGN 128 | #define DBA_ALIGN 128 | ||||
/* | /* | ||||
* This parameter controls the maximum no of times the driver will loop in | |||||
* the isr. Minimum Value = 1 | |||||
*/ | |||||
#define MAX_LOOP 10 | |||||
/* | |||||
* This is the max watchdog interval, ie. the time that can | * This is the max watchdog interval, ie. the time that can | ||||
* pass between any two TX clean operations, such only happening | * pass between any two TX clean operations, such only happening | ||||
* when the TX hardware is functioning. | * when the TX hardware is functioning. | ||||
*/ | */ | ||||
#define IXL_WATCHDOG (10 * hz) | #define IXL_WATCHDOG (10 * hz) | ||||
/* | /* | ||||
* This parameters control when the driver calls the routine to reclaim | * This parameters control when the driver calls the routine to reclaim | ||||
* transmit descriptors. | * transmit descriptors. | ||||
*/ | */ | ||||
#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8) | #define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8) | ||||
#define IXL_TX_OP_THRESHOLD (que->num_desc / 32) | #define IXL_TX_OP_THRESHOLD (que->num_desc / 32) | ||||
/* Flow control constants */ | /* Flow control constants */ | ||||
#define IXL_FC_PAUSE 0xFFFF | #define IXL_FC_PAUSE 0xFFFF | ||||
#define IXL_FC_HI 0x20000 | #define IXL_FC_HI 0x20000 | ||||
#define IXL_FC_LO 0x10000 | #define IXL_FC_LO 0x10000 | ||||
#define MAX_MULTICAST_ADDR 128 | #define MAX_MULTICAST_ADDR 128 | ||||
#define IXL_BAR 3 | #define IXL_BAR 3 | ||||
#define IXL_ADM_LIMIT 2 | #define IXL_ADM_LIMIT 2 | ||||
#define IXL_TSO_SIZE 65535 | #define IXL_TSO_SIZE 65535 | ||||
#define IXL_TX_BUF_SZ ((u32) 1514) | |||||
#define IXL_AQ_BUF_SZ ((u32) 4096) | #define IXL_AQ_BUF_SZ ((u32) 4096) | ||||
#define IXL_RX_HDR 128 | #define IXL_RX_HDR 128 | ||||
/* Controls the length of the Admin Queue */ | /* Controls the length of the Admin Queue */ | ||||
#define IXL_AQ_LEN 256 | #define IXL_AQ_LEN 256 | ||||
#define IXL_AQ_LEN_MAX 1024 | #define IXL_AQ_LEN_MAX 1024 | ||||
#define IXL_AQ_BUFSZ 4096 | #define IXL_AQ_BUFSZ 4096 | ||||
#define IXL_RX_LIMIT 512 | #define IXL_RX_LIMIT 512 | ||||
#define IXL_RX_ITR 0 | #define IXL_RX_ITR 0 | ||||
#define IXL_TX_ITR 1 | #define IXL_TX_ITR 1 | ||||
#define IXL_ITR_NONE 3 | #define IXL_ITR_NONE 3 | ||||
#define IXL_QUEUE_EOL 0x7FF | #define IXL_QUEUE_EOL 0x7FF | ||||
#define IXL_MAX_FRAME 0x2600 | #define IXL_MAX_FRAME 9728 | ||||
#define IXL_MAX_TX_SEGS 8 | #define IXL_MAX_TX_SEGS 8 | ||||
#define IXL_MAX_TSO_SEGS 66 | #define IXL_MAX_TSO_SEGS 66 | ||||
#define IXL_SPARSE_CHAIN 6 | #define IXL_SPARSE_CHAIN 6 | ||||
#define IXL_QUEUE_HUNG 0x80000000 | #define IXL_QUEUE_HUNG 0x80000000 | ||||
#define IXL_KEYSZ 10 | #define IXL_KEYSZ 10 | ||||
#define IXL_VF_MAX_BUFFER 0x3F80 | #define IXL_VF_MAX_BUFFER 0x3F80 | ||||
#define IXL_VF_MAX_HDR_BUFFER 0x840 | #define IXL_VF_MAX_HDR_BUFFER 0x840 | ||||
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#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) | #define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) | ||||
#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx) | #define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx) | ||||
#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) | #define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) | ||||
#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx) | #define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx) | ||||
#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) | #define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) | ||||
#define IXL_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) | #define IXL_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) | ||||
/* Pre-11 counter(9) compatibility */ | |||||
#if __FreeBSD_version >= 1100036 | #if __FreeBSD_version >= 1100036 | ||||
#define IXL_SET_IPACKETS(vsi, count) (vsi)->ipackets = (count) | #define IXL_SET_IPACKETS(vsi, count) (vsi)->ipackets = (count) | ||||
#define IXL_SET_IERRORS(vsi, count) (vsi)->ierrors = (count) | #define IXL_SET_IERRORS(vsi, count) (vsi)->ierrors = (count) | ||||
#define IXL_SET_OPACKETS(vsi, count) (vsi)->opackets = (count) | #define IXL_SET_OPACKETS(vsi, count) (vsi)->opackets = (count) | ||||
#define IXL_SET_OERRORS(vsi, count) (vsi)->oerrors = (count) | #define IXL_SET_OERRORS(vsi, count) (vsi)->oerrors = (count) | ||||
#define IXL_SET_COLLISIONS(vsi, count) /* Do nothing; collisions is always 0. */ | #define IXL_SET_COLLISIONS(vsi, count) /* Do nothing; collisions is always 0. */ | ||||
#define IXL_SET_IBYTES(vsi, count) (vsi)->ibytes = (count) | #define IXL_SET_IBYTES(vsi, count) (vsi)->ibytes = (count) | ||||
#define IXL_SET_OBYTES(vsi, count) (vsi)->obytes = (count) | #define IXL_SET_OBYTES(vsi, count) (vsi)->obytes = (count) | ||||
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#define IXL_SET_OBYTES(vsi, count) (vsi)->ifp->if_obytes = (count) | #define IXL_SET_OBYTES(vsi, count) (vsi)->ifp->if_obytes = (count) | ||||
#define IXL_SET_IMCASTS(vsi, count) (vsi)->ifp->if_imcasts = (count) | #define IXL_SET_IMCASTS(vsi, count) (vsi)->ifp->if_imcasts = (count) | ||||
#define IXL_SET_OMCASTS(vsi, count) (vsi)->ifp->if_omcasts = (count) | #define IXL_SET_OMCASTS(vsi, count) (vsi)->ifp->if_omcasts = (count) | ||||
#define IXL_SET_IQDROPS(vsi, count) (vsi)->ifp->if_iqdrops = (count) | #define IXL_SET_IQDROPS(vsi, count) (vsi)->ifp->if_iqdrops = (count) | ||||
#define IXL_SET_OQDROPS(vsi, odrops) (vsi)->ifp->if_snd.ifq_drops = (odrops) | #define IXL_SET_OQDROPS(vsi, odrops) (vsi)->ifp->if_snd.ifq_drops = (odrops) | ||||
#define IXL_SET_NOPROTO(vsi, count) (vsi)->noproto = (count) | #define IXL_SET_NOPROTO(vsi, count) (vsi)->noproto = (count) | ||||
#endif | #endif | ||||
/* Pre-10.2 media type compatibility */ | |||||
#if __FreeBSD_version < 1002000 | |||||
#define IFM_OTHER IFM_UNKNOWN | |||||
#endif | |||||
/* | /* | ||||
***************************************************************************** | ***************************************************************************** | ||||
* vendor_info_array | * vendor_info_array | ||||
* | * | ||||
* This array contains the list of Subvendor/Subdevice IDs on which the driver | * This array contains the list of Subvendor/Subdevice IDs on which the driver | ||||
* should load. | * should load. | ||||
* | * | ||||
***************************************************************************** | ***************************************************************************** | ||||
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*/ | */ | ||||
struct ixl_mac_filter { | struct ixl_mac_filter { | ||||
SLIST_ENTRY(ixl_mac_filter) next; | SLIST_ENTRY(ixl_mac_filter) next; | ||||
u8 macaddr[ETHER_ADDR_LEN]; | u8 macaddr[ETHER_ADDR_LEN]; | ||||
s16 vlan; | s16 vlan; | ||||
u16 flags; | u16 flags; | ||||
}; | }; | ||||
/* | /* | ||||
* The Transmit ring control struct | * The Transmit ring control struct | ||||
*/ | */ | ||||
struct tx_ring { | struct tx_ring { | ||||
struct ixl_queue *que; | struct ixl_queue *que; | ||||
struct mtx mtx; | struct mtx mtx; | ||||
u32 tail; | u32 tail; | ||||
struct i40e_tx_desc *base; | struct i40e_tx_desc *base; | ||||
struct i40e_dma_mem dma; | struct i40e_dma_mem dma; | ||||
u16 next_avail; | u16 next_avail; | ||||
u16 next_to_clean; | u16 next_to_clean; | ||||
u16 atr_rate; | u16 atr_rate; | ||||
u16 atr_count; | u16 atr_count; | ||||
u16 itr; | u32 itr; | ||||
u16 latency; | u32 latency; | ||||
struct ixl_tx_buf *buffers; | struct ixl_tx_buf *buffers; | ||||
volatile u16 avail; | volatile u16 avail; | ||||
u32 cmd; | u32 cmd; | ||||
bus_dma_tag_t tx_tag; | bus_dma_tag_t tx_tag; | ||||
bus_dma_tag_t tso_tag; | bus_dma_tag_t tso_tag; | ||||
char mtx_name[16]; | char mtx_name[16]; | ||||
struct buf_ring *br; | struct buf_ring *br; | ||||
Show All 15 Lines | struct rx_ring { | ||||
struct ixl_queue *que; | struct ixl_queue *que; | ||||
struct mtx mtx; | struct mtx mtx; | ||||
union i40e_rx_desc *base; | union i40e_rx_desc *base; | ||||
struct i40e_dma_mem dma; | struct i40e_dma_mem dma; | ||||
struct lro_ctrl lro; | struct lro_ctrl lro; | ||||
bool lro_enabled; | bool lro_enabled; | ||||
bool hdr_split; | bool hdr_split; | ||||
bool discard; | bool discard; | ||||
u16 next_refresh; | u32 next_refresh; | ||||
u16 next_check; | u32 next_check; | ||||
u16 itr; | u32 itr; | ||||
u16 latency; | u32 latency; | ||||
char mtx_name[16]; | char mtx_name[16]; | ||||
struct ixl_rx_buf *buffers; | struct ixl_rx_buf *buffers; | ||||
u32 mbuf_sz; | u32 mbuf_sz; | ||||
u32 tail; | u32 tail; | ||||
bus_dma_tag_t htag; | bus_dma_tag_t htag; | ||||
bus_dma_tag_t ptag; | bus_dma_tag_t ptag; | ||||
/* Used for Dynamic ITR calculation */ | /* Used for Dynamic ITR calculation */ | ||||
u32 packets; | u32 packets; | ||||
u32 bytes; | u32 bytes; | ||||
/* Soft stats */ | /* Soft stats */ | ||||
u64 split; | u64 split; | ||||
u64 rx_packets; | u64 rx_packets; | ||||
u64 rx_bytes; | u64 rx_bytes; | ||||
u64 discarded; | u64 desc_errs; | ||||
u64 not_done; | u64 not_done; | ||||
}; | }; | ||||
/* | /* | ||||
** Driver queue struct: this is the interrupt container | ** Driver queue struct: this is the interrupt container | ||||
** for the associated tx and rx ring pair. | ** for the associated tx and rx ring pair. | ||||
*/ | */ | ||||
struct ixl_queue { | struct ixl_queue { | ||||
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*/ | */ | ||||
SLIST_HEAD(ixl_ftl_head, ixl_mac_filter); | SLIST_HEAD(ixl_ftl_head, ixl_mac_filter); | ||||
struct ixl_vsi { | struct ixl_vsi { | ||||
void *back; | void *back; | ||||
struct ifnet *ifp; | struct ifnet *ifp; | ||||
struct device *dev; | struct device *dev; | ||||
struct i40e_hw *hw; | struct i40e_hw *hw; | ||||
struct ifmedia media; | struct ifmedia media; | ||||
enum i40e_vsi_type type; | |||||
u64 que_mask; | u64 que_mask; | ||||
int id; | int id; | ||||
u16 vsi_num; | u16 vsi_num; | ||||
u16 msix_base; /* station base MSIX vector */ | u16 msix_base; /* station base MSIX vector */ | ||||
u16 first_queue; | u16 first_queue; | ||||
u16 num_queues; | u16 num_queues; | ||||
u16 rx_itr_setting; | u32 rx_itr_setting; | ||||
u16 tx_itr_setting; | u32 tx_itr_setting; | ||||
struct ixl_queue *queues; /* head of queues */ | struct ixl_queue *queues; /* head of queues */ | ||||
bool link_active; | bool link_active; | ||||
u16 seid; | u16 seid; | ||||
u16 uplink_seid; | u16 uplink_seid; | ||||
u16 downlink_seid; | u16 downlink_seid; | ||||
u16 max_frame_size; | u16 max_frame_size; | ||||
u16 rss_table_size; | |||||
u16 rss_size; | |||||
/* MAC/VLAN Filter list */ | /* MAC/VLAN Filter list */ | ||||
struct ixl_ftl_head ftl; | struct ixl_ftl_head ftl; | ||||
u16 num_macs; | u16 num_macs; | ||||
struct i40e_aqc_vsi_properties_data info; | struct i40e_aqc_vsi_properties_data info; | ||||
eventhandler_tag vlan_attach; | eventhandler_tag vlan_attach; | ||||
eventhandler_tag vlan_detach; | eventhandler_tag vlan_detach; | ||||
u16 num_vlans; | u16 num_vlans; | ||||
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*/ | */ | ||||
struct ixl_sysctl_info { | struct ixl_sysctl_info { | ||||
u64 *stat; | u64 *stat; | ||||
char *name; | char *name; | ||||
char *description; | char *description; | ||||
}; | }; | ||||
extern int ixl_atr_rate; | extern int ixl_atr_rate; | ||||
/* | |||||
** ixl_fw_version_str - format the FW and NVM version strings | |||||
*/ | |||||
static inline char * | |||||
ixl_fw_version_str(struct i40e_hw *hw) | |||||
{ | |||||
static char buf[32]; | |||||
snprintf(buf, sizeof(buf), | |||||
"f%d.%d a%d.%d n%02x.%02x e%08x", | |||||
hw->aq.fw_maj_ver, hw->aq.fw_min_ver, | |||||
hw->aq.api_maj_ver, hw->aq.api_min_ver, | |||||
(hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> | |||||
IXL_NVM_VERSION_HI_SHIFT, | |||||
(hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> | |||||
IXL_NVM_VERSION_LO_SHIFT, | |||||
hw->nvm.eetrack); | |||||
return buf; | |||||
} | |||||
/********************************************************************* | /********************************************************************* | ||||
* TXRX Function prototypes | * TXRX Function prototypes | ||||
*********************************************************************/ | *********************************************************************/ | ||||
int ixl_allocate_tx_data(struct ixl_queue *); | int ixl_allocate_tx_data(struct ixl_queue *); | ||||
int ixl_allocate_rx_data(struct ixl_queue *); | int ixl_allocate_rx_data(struct ixl_queue *); | ||||
void ixl_init_tx_ring(struct ixl_queue *); | void ixl_init_tx_ring(struct ixl_queue *); | ||||
int ixl_init_rx_ring(struct ixl_queue *); | int ixl_init_rx_ring(struct ixl_queue *); | ||||
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