Differential D6211 Diff 15908 sys/dev/ixl/i40e_register.h

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sys/dev/ixl/i40e_register.h

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	#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31			#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
	#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)			#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
	#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */			#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */
	#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0			#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
	#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)			#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
	#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */			#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */
	#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0			#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
	#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)			#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
				#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) /* _i=0...3 / / Reset: CORER */
				#define I40E_GL_PRS_FVBM_MAX_INDEX 3
				#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT 0
				#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)
				#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8
				#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT)
				#define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT 31
				#define I40E_GL_PRS_FVBM_MSK_ENA_MASK I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)
	#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */			#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */
	#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0			#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
	#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)			#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
	#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */			#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */
	#define I40E_GLRPB_GHW_GHW_SHIFT 0			#define I40E_GLRPB_GHW_GHW_SHIFT 0
	#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)			#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
	#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */			#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */
	#define I40E_GLRPB_GLW_GLW_SHIFT 0			#define I40E_GLRPB_GLW_GLW_SHIFT 0
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	#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)			#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)
	#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */			#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */
	#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0			#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0
	#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)			#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
	#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 / / Reset: CORER */			#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 / / Reset: CORER */
	#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63			#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63
	#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0			#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
	#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)			#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
				#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 / / Reset: CORER */
				#define I40E_PRTQF_FD_INSET_MAX_INDEX 63
				#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
				#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
				#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 / / Reset: CORER */
				#define I40E_PRTQF_FD_INSET_MAX_INDEX 63
				#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
				#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
	#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 / / Reset: CORER */			#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 / / Reset: CORER */
	#define I40E_PRTQF_FD_MSK_MAX_INDEX 63			#define I40E_PRTQF_FD_MSK_MAX_INDEX 63
	#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0			#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0
	#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)			#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)
	#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16			#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16
	#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)			#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
	#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 / / Reset: CORER */			#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 / / Reset: CORER */
	#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8			#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8
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	#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24			#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
	#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)			#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
	#define I40E_VFQF_HREGION_REGION_6_SHIFT 25			#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
	#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)			#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
	#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28			#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
	#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)			#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
	#define I40E_VFQF_HREGION_REGION_7_SHIFT 29			#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
	#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)			#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
	#ifdef X722_SUPPORT

	#define I40E_MNGSB_FDCRC 0x000B7050 /* Reset: POR */
	#define I40E_MNGSB_FDCRC_CRC_RES_SHIFT 0
	#define I40E_MNGSB_FDCRC_CRC_RES_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCRC_CRC_RES_SHIFT)
	#define I40E_MNGSB_FDCS 0x000B7040 /* Reset: POR */
	#define I40E_MNGSB_FDCS_CRC_CONT_SHIFT 2
	#define I40E_MNGSB_FDCS_CRC_CONT_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_CONT_SHIFT)
	#define I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT 3
	#define I40E_MNGSB_FDCS_CRC_SEED_EN_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT)
	#define I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT 4
	#define I40E_MNGSB_FDCS_CRC_WR_INH_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT)
	#define I40E_MNGSB_FDCS_CRC_SEED_SHIFT 8
	#define I40E_MNGSB_FDCS_CRC_SEED_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCS_CRC_SEED_SHIFT)
	#define I40E_MNGSB_FDS 0x000B7048 /* Reset: POR */
	#define I40E_MNGSB_FDS_START_BC_SHIFT 0
	#define I40E_MNGSB_FDS_START_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_START_BC_SHIFT)
	#define I40E_MNGSB_FDS_LAST_BC_SHIFT 16
	#define I40E_MNGSB_FDS_LAST_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_LAST_BC_SHIFT)

	#define I40E_GL_VF_CTRL_RX(_VF) (0x00083600 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	#define I40E_GL_VF_CTRL_RX_MAX_INDEX 127
	#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT 0
	#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT)
	#define I40E_GL_VF_CTRL_TX(_VF) (0x00083400 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	#define I40E_GL_VF_CTRL_TX_MAX_INDEX 127
	#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT 0
	#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT)

	#define I40E_GLCM_LAN_CACHESIZE 0x0010C4D8 /* Reset: CORER */
	#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT 0
	#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT)
	#define I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT 12
	#define I40E_GLCM_LAN_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT)
	#define I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT 16
	#define I40E_GLCM_LAN_CACHESIZE_WAYS_MASK I40E_MASK(0x3FF, I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT)
	#define I40E_GLCM_PE_CACHESIZE 0x00138FE4 /* Reset: CORER */
	#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT 0
	#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT)
	#define I40E_GLCM_PE_CACHESIZE_SETS_SHIFT 12
	#define I40E_GLCM_PE_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_PE_CACHESIZE_SETS_SHIFT)
	#define I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT 16
	#define I40E_GLCM_PE_CACHESIZE_WAYS_MASK I40E_MASK(0x1FF, I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT)
	#define I40E_PFCM_PE_ERRDATA 0x00138D00 /* Reset: PFR */
	#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
	#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
	#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
	#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
	#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8
	#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
	#define I40E_PFCM_PE_ERRINFO 0x00138C80 /* Reset: PFR */
	#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
	#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
	#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
	#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
	#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
	#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
	#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
	#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
	#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
	#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)

	#define I40E_PRTDCB_TFMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 / / Reset: CORER */
	#define I40E_PRTDCB_TFMSTC_MAX_INDEX 7
	#define I40E_PRTDCB_TFMSTC_MSTC_SHIFT 0
	#define I40E_PRTDCB_TFMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TFMSTC_MSTC_SHIFT)
	#define I40E_GL_FWSTS_FWROWD_SHIFT 8
	#define I40E_GL_FWSTS_FWROWD_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWROWD_SHIFT)
	#define I40E_GLFOC_CACHESIZE 0x000AA0DC /* Reset: CORER */
	#define I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT 0
	#define I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT)
	#define I40E_GLFOC_CACHESIZE_SETS_SHIFT 8
	#define I40E_GLFOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLFOC_CACHESIZE_SETS_SHIFT)
	#define I40E_GLFOC_CACHESIZE_WAYS_SHIFT 20
	#define I40E_GLFOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLFOC_CACHESIZE_WAYS_SHIFT)
	#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15
	#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
	#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
	#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_CEQPART_MAX_INDEX 15
	#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0
	#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
	#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16
	#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
	#define I40E_GLHMC_DBCQMAX 0x000C20F0 /* Reset: CORER */
	#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT 0
	#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK I40E_MASK(0x3FFFF, I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT)
	#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_DBCQPART_MAX_INDEX 15
	#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0
	#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
	#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16
	#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
	#define I40E_GLHMC_DBQPMAX 0x000C20EC /* Reset: CORER */
	#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT 0
	#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK I40E_MASK(0x7FFFF, I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT)
	#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_DBQPPART_MAX_INDEX 15
	#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0
	#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
	#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16
	#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
	#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0
	#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
	#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15
	#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0
	#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
	#define I40E_GLHMC_PEARPMAX 0x000C2038 /* Reset: CORER */
	#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0
	#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
	#define I40E_GLHMC_PEARPOBJSZ 0x000C2034 /* Reset: CORER */
	#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0
	#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK I40E_MASK(0x7, I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
	#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PECQBASE_MAX_INDEX 15
	#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0
	#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
	#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PECQCNT_MAX_INDEX 15
	#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0
	#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
	#define I40E_GLHMC_PECQOBJSZ 0x000C2020 /* Reset: CORER */
	#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0
	#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
	#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15
	#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0
	#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
	#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0
	#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
	#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c /* Reset: CORER */
	#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0
	#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
	#define I40E_GLHMC_PEHTMAX 0x000C2030 /* Reset: CORER */
	#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0
	#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK I40E_MASK(0x1FFFFF, I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
	#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0
	#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
	#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15
	#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0
	#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
	#define I40E_GLHMC_PEMRMAX 0x000C2040 /* Reset: CORER */
	#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0
	#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
	#define I40E_GLHMC_PEMROBJSZ 0x000C203c /* Reset: CORER */
	#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0
	#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
	#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0
	#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
	#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15
	#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0
	#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
	#define I40E_GLHMC_PEPBLMAX 0x000C206c /* Reset: CORER */
	#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0
	#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
	#define I40E_GLHMC_PEPFFIRSTSD 0x000C20E4 /* Reset: CORER */
	#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT 0
	#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK I40E_MASK(0xFFF, I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT)
	#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15
	#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0
	#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
	#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15
	#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0
	#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
	#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
	#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
	#define I40E_GLHMC_PEQ1FLMAX 0x000C2058 /* Reset: CORER */
	#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
	#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
	#define I40E_GLHMC_PEQ1MAX 0x000C2054 /* Reset: CORER */
	#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
	#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
	#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 /* Reset: CORER */
	#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0
	#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
	#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0
	#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
	#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15
	#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0
	#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
	#define I40E_GLHMC_PEQPOBJSZ 0x000C201c /* Reset: CORER */
	#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0
	#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
	#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15
	#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0
	#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
	#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15
	#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0
	#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
	#define I40E_GLHMC_PESRQMAX 0x000C2028 /* Reset: CORER */
	#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0
	#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
	#define I40E_GLHMC_PESRQOBJSZ 0x000C2024 /* Reset: CORER */
	#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0
	#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
	#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15
	#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0
	#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
	#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15
	#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0
	#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
	#define I40E_GLHMC_PETIMERMAX 0x000C2084 /* Reset: CORER */
	#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0
	#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
	#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 /* Reset: CORER */
	#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0
	#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
	#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0
	#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
	#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15
	#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0
	#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
	#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15
	#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
	#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
	#define I40E_GLHMC_PEXFFLMAX 0x000C204c /* Reset: CORER */
	#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
	#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK I40E_MASK(0x1FFFFFF, I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
	#define I40E_GLHMC_PEXFMAX 0x000C2048 /* Reset: CORER */
	#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
	#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
	#define I40E_GLHMC_PEXFOBJSZ 0x000C2044 /* Reset: CORER */
	#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0
	#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
	#define I40E_GLHMC_PFPESDPART(_i) (0x000C0880 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLHMC_PFPESDPART_MAX_INDEX 15
	#define I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT 0
	#define I40E_GLHMC_PFPESDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT)
	#define I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT 16
	#define I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT)
	#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
	#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
	#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31
	#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0
	#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
	#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16
	#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
	#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31
	#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0
	#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
	#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16
	#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
	#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31
	#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0
	#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
	#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16
	#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
	#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0
	#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
	#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0
	#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
	#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPDINV_MAX_INDEX 31
	#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0
	#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
	#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT 15
	#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT)
	#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16
	#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
	#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0
	#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
	#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0
	#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
	#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0
	#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
	#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0
	#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
	#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0
	#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
	#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0
	#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
	#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0
	#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
	#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0
	#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
	#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0
	#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
	#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0
	#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
	#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0
	#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
	#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0
	#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
	#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
	#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
	#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0
	#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
	#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0
	#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
	#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0
	#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
	#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0
	#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
	#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0
	#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
	#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0
	#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
	#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0
	#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
	#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31
	#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0
	#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
	#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31
	#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
	#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
	#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLHMC_VFSDPART_MAX_INDEX 31
	#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0
	#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
	#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16
	#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
	#define I40E_GLPBLOC_CACHESIZE 0x000A80BC /* Reset: CORER */
	#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT 0
	#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT)
	#define I40E_GLPBLOC_CACHESIZE_SETS_SHIFT 8
	#define I40E_GLPBLOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPBLOC_CACHESIZE_SETS_SHIFT)
	#define I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT 20
	#define I40E_GLPBLOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT)
	#define I40E_GLPDOC_CACHESIZE 0x000D0088 /* Reset: CORER */
	#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT 0
	#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT)
	#define I40E_GLPDOC_CACHESIZE_SETS_SHIFT 8
	#define I40E_GLPDOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPDOC_CACHESIZE_SETS_SHIFT)
	#define I40E_GLPDOC_CACHESIZE_WAYS_SHIFT 20
	#define I40E_GLPDOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPDOC_CACHESIZE_WAYS_SHIFT)
	#define I40E_GLPEOC_CACHESIZE 0x000A60E8 /* Reset: CORER */
	#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT 0
	#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT)
	#define I40E_GLPEOC_CACHESIZE_SETS_SHIFT 8
	#define I40E_GLPEOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPEOC_CACHESIZE_SETS_SHIFT)
	#define I40E_GLPEOC_CACHESIZE_WAYS_SHIFT 20
	#define I40E_GLPEOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPEOC_CACHESIZE_WAYS_SHIFT)
	#define I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT 15
	#define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT)
	#define I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT 15
	#define I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT)
	#define I40E_GL_PPRS_SPARE 0x000856E0 /* Reset: CORER */
	#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT 0
	#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT)
	#define I40E_GL_TLAN_SPARE 0x000E64E0 /* Reset: CORER */
	#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT 0
	#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT)
	#define I40E_GL_TUPM_SPARE 0x000a2230 /* Reset: CORER */
	#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT 0
	#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG 0x000B81C0 /* Reset: POR */
	#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT 0
	#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT 1
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT 2
	#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT 3
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT 4
	#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT 5
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT 6
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT 7
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT 8
	#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT 9
	#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT 10
	#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT 11
	#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT 12
	#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT 13
	#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT)
	#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT 14
	#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT)
	#define I40E_GLGEN_MISC_SPARE 0x000880E0 /* Reset: POR */
	#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT 0
	#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT)
	#define I40E_GL_UFUSE_SOC 0x000BE550 /* Reset: POR */
	#define I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT 0
	#define I40E_GL_UFUSE_SOC_PORT_MODE_MASK I40E_MASK(0x3, I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT)
	#define I40E_GL_UFUSE_SOC_NIC_ID_SHIFT 2
	#define I40E_GL_UFUSE_SOC_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_SOC_NIC_ID_SHIFT)
	#define I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT 3
	#define I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK I40E_MASK(0x1FFF, I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT)
	#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
	#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
	#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
	#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
	#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
	#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
	#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
	#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
	#define I40E_VPLAN_QBASE(_VF) (0x00074800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VPLAN_QBASE_MAX_INDEX 127
	#define I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT 0
	#define I40E_VPLAN_QBASE_VFFIRSTQ_MASK I40E_MASK(0x7FF, I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT)
	#define I40E_VPLAN_QBASE_VFNUMQ_SHIFT 11
	#define I40E_VPLAN_QBASE_VFNUMQ_MASK I40E_MASK(0xFF, I40E_VPLAN_QBASE_VFNUMQ_SHIFT)
	#define I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT 31
	#define I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT)
	#define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */
	#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT 0
	#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT)
	#define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */
	#define I40E_GLNVM_AL_REQ_POR_SHIFT 0
	#define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_POR_SHIFT)
	#define I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT 1
	#define I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT)
	#define I40E_GLNVM_AL_REQ_GLOBR_SHIFT 2
	#define I40E_GLNVM_AL_REQ_GLOBR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_GLOBR_SHIFT)
	#define I40E_GLNVM_AL_REQ_CORER_SHIFT 3
	#define I40E_GLNVM_AL_REQ_CORER_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_CORER_SHIFT)
	#define I40E_GLNVM_AL_REQ_PE_SHIFT 4
	#define I40E_GLNVM_AL_REQ_PE_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PE_SHIFT)
	#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT 5
	#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT)
	#define I40E_GLNVM_ALTIMERS 0x000B6140 /* Reset: POR */
	#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT 0
	#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT)
	#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT 12
	#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT)
	#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
	#define I40E_GLNVM_FLA_LOCKED_SHIFT 6
	#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)

	#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
	#define I40E_GLNVM_ULD_PCIER_DONE_SHIFT 0
	#define I40E_GLNVM_ULD_PCIER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_SHIFT)
	#define I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT 1
	#define I40E_GLNVM_ULD_PCIER_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT)
	#define I40E_GLNVM_ULD_CORER_DONE_SHIFT 3
	#define I40E_GLNVM_ULD_CORER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CORER_DONE_SHIFT)
	#define I40E_GLNVM_ULD_GLOBR_DONE_SHIFT 4
	#define I40E_GLNVM_ULD_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_GLOBR_DONE_SHIFT)
	#define I40E_GLNVM_ULD_POR_DONE_SHIFT 5
	#define I40E_GLNVM_ULD_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_SHIFT)
	#define I40E_GLNVM_ULD_POR_DONE_1_SHIFT 8
	#define I40E_GLNVM_ULD_POR_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_1_SHIFT)
	#define I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT 9
	#define I40E_GLNVM_ULD_PCIER_DONE_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT)
	#define I40E_GLNVM_ULD_PE_DONE_SHIFT 10
	#define I40E_GLNVM_ULD_PE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PE_DONE_SHIFT)
	#define I40E_GLNVM_ULT 0x000B6154 /* Reset: POR */
	#define I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT 0
	#define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT)
	#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT 1
	#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT)
	#define I40E_GLNVM_ULT_RESERVED_1_SHIFT 2
	#define I40E_GLNVM_ULT_RESERVED_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_1_SHIFT)
	#define I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT 3
	#define I40E_GLNVM_ULT_CONF_CORE_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT)
	#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT 4
	#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT)
	#define I40E_GLNVM_ULT_CONF_POR_AE_SHIFT 5
	#define I40E_GLNVM_ULT_CONF_POR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_POR_AE_SHIFT)
	#define I40E_GLNVM_ULT_RESERVED_2_SHIFT 6
	#define I40E_GLNVM_ULT_RESERVED_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_2_SHIFT)
	#define I40E_GLNVM_ULT_RESERVED_3_SHIFT 7
	#define I40E_GLNVM_ULT_RESERVED_3_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_3_SHIFT)
	#define I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT 8
	#define I40E_GLNVM_ULT_CONF_EMP_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT)
	#define I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT 9
	#define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT)
	#define I40E_GLNVM_ULT_RESERVED_4_SHIFT 10
	#define I40E_GLNVM_ULT_RESERVED_4_MASK I40E_MASK(0x3FFFFF, I40E_GLNVM_ULT_RESERVED_4_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT 0x000B615C /* Reset: POR */
	#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT 0
	#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT 1
	#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT 2
	#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT 3
	#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT 4
	#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT 5
	#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT 6
	#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT 7
	#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT 8
	#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT 9
	#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT 10
	#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT 11
	#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT 12
	#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT 13
	#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT 14
	#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT 15
	#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT)
	#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT 16
	#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT)
	#define I40E_MNGSB_DADD 0x000B7030 /* Reset: POR */
	#define I40E_MNGSB_DADD_ADDR_SHIFT 0
	#define I40E_MNGSB_DADD_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DADD_ADDR_SHIFT)
	#define I40E_MNGSB_DCNT 0x000B7034 /* Reset: POR */
	#define I40E_MNGSB_DCNT_BYTE_CNT_SHIFT 0
	#define I40E_MNGSB_DCNT_BYTE_CNT_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DCNT_BYTE_CNT_SHIFT)
	#define I40E_MNGSB_MSGCTL 0x000B7020 /* Reset: POR */
	#define I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT 0
	#define I40E_MNGSB_MSGCTL_HDR_DWS_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT)
	#define I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT 8
	#define I40E_MNGSB_MSGCTL_EXP_RDW_MASK I40E_MASK(0x1FF, I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT)
	#define I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT 26
	#define I40E_MNGSB_MSGCTL_MSG_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT)
	#define I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT 28
	#define I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT)
	#define I40E_MNGSB_MSGCTL_BARCLR_SHIFT 30
	#define I40E_MNGSB_MSGCTL_BARCLR_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_BARCLR_SHIFT)
	#define I40E_MNGSB_MSGCTL_CMDV_SHIFT 31
	#define I40E_MNGSB_MSGCTL_CMDV_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_CMDV_SHIFT)
	#define I40E_MNGSB_RDATA 0x000B7300 /* Reset: POR */
	#define I40E_MNGSB_RDATA_DATA_SHIFT 0
	#define I40E_MNGSB_RDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_RDATA_DATA_SHIFT)
	#define I40E_MNGSB_RHDR0 0x000B72FC /* Reset: POR */
	#define I40E_MNGSB_RHDR0_DESTINATION_SHIFT 0
	#define I40E_MNGSB_RHDR0_DESTINATION_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_DESTINATION_SHIFT)
	#define I40E_MNGSB_RHDR0_SOURCE_SHIFT 8
	#define I40E_MNGSB_RHDR0_SOURCE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_SOURCE_SHIFT)
	#define I40E_MNGSB_RHDR0_OPCODE_SHIFT 16
	#define I40E_MNGSB_RHDR0_OPCODE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_OPCODE_SHIFT)
	#define I40E_MNGSB_RHDR0_TAG_SHIFT 24
	#define I40E_MNGSB_RHDR0_TAG_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_TAG_SHIFT)
	#define I40E_MNGSB_RHDR0_RESPONSE_SHIFT 27
	#define I40E_MNGSB_RHDR0_RESPONSE_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_RESPONSE_SHIFT)
	#define I40E_MNGSB_RHDR0_EH_SHIFT 31
	#define I40E_MNGSB_RHDR0_EH_MASK I40E_MASK(0x1, I40E_MNGSB_RHDR0_EH_SHIFT)
	#define I40E_MNGSB_RSPCTL 0x000B7024 /* Reset: POR */
	#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT 0
	#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK I40E_MASK(0x1FF, I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT)
	#define I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT 26
	#define I40E_MNGSB_RSPCTL_RSP_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT)
	#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT 30
	#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT)
	#define I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT 31
	#define I40E_MNGSB_RSPCTL_RSP_ERR_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT)
	#define I40E_MNGSB_WDATA 0x000B7100 /* Reset: POR */
	#define I40E_MNGSB_WDATA_DATA_SHIFT 0
	#define I40E_MNGSB_WDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WDATA_DATA_SHIFT)
	#define I40E_MNGSB_WHDR0 0x000B70F4 /* Reset: POR */
	#define I40E_MNGSB_WHDR0_RAW_DEST_SHIFT 0
	#define I40E_MNGSB_WHDR0_RAW_DEST_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_RAW_DEST_SHIFT)
	#define I40E_MNGSB_WHDR0_DEST_SEL_SHIFT 12
	#define I40E_MNGSB_WHDR0_DEST_SEL_MASK I40E_MASK(0xF, I40E_MNGSB_WHDR0_DEST_SEL_SHIFT)
	#define I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT 16
	#define I40E_MNGSB_WHDR0_OPCODE_SEL_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT)
	#define I40E_MNGSB_WHDR0_TAG_SHIFT 24
	#define I40E_MNGSB_WHDR0_TAG_MASK I40E_MASK(0x7F, I40E_MNGSB_WHDR0_TAG_SHIFT)
	#define I40E_MNGSB_WHDR1 0x000B70F8 /* Reset: POR */
	#define I40E_MNGSB_WHDR1_ADDR_SHIFT 0
	#define I40E_MNGSB_WHDR1_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR1_ADDR_SHIFT)
	#define I40E_MNGSB_WHDR2 0x000B70FC /* Reset: POR */
	#define I40E_MNGSB_WHDR2_LENGTH_SHIFT 0
	#define I40E_MNGSB_WHDR2_LENGTH_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR2_LENGTH_SHIFT)

	#define I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT 21
	#define I40E_GLPCI_CAPSUP_WAKUP_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT)

	#define I40E_GLPCI_CUR_CLNT_COMMON 0x0009CA18 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT)
	#define I40E_GLPCI_CUR_CLNT_PIPEMON 0x0009CA20 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_MNG_ALWD 0x0009c514 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_MNG_RSVD 0x0009c594 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_PMAT_ALWD 0x0009c510 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_PMAT_RSVD 0x0009c590 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_RLAN_ALWD 0x0009c500 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_RLAN_RSVD 0x0009c580 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_RXPE_ALWD 0x0009c508 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_RXPE_RSVD 0x0009c588 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_TDPU_ALWD 0x0009c518 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_TDPU_RSVD 0x0009c598 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_TLAN_ALWD 0x0009c504 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_TLAN_RSVD 0x0009c584 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_TXPE_ALWD 0x0009c50C /* Reset: PCIR */
	#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_TXPE_RSVD 0x0009c58c /* Reset: PCIR */
	#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT)
	#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON 0x0009CA28 /* Reset: PCIR */
	#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT)
	#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT 16
	#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT)

	#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4
	#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT)
	#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10
	#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT)
	#define I40E_GLPCI_NPQ_CFG 0x0009CA00 /* Reset: PCIR */
	#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT 0
	#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT)
	#define I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT 1
	#define I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT)
	#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT 2
	#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT)
	#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT 6
	#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK I40E_MASK(0x3FF, I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT)
	#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT 16
	#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT)
	#define I40E_GLPCI_WATMK_CLNT_PIPEMON 0x0009CA30 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_MNG_ALWD 0x0009CB14 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_WATMK_PMAT_ALWD 0x0009CB10 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_WATMK_RLAN_ALWD 0x0009CB00 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_WATMK_RXPE_ALWD 0x0009CB08 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_WATMK_TLAN_ALWD 0x0009CB04 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_WATMK_TPDU_ALWD 0x0009CB18 /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT)
	#define I40E_GLPCI_WATMK_TXPE_ALWD 0x0009CB0c /* Reset: PCIR */
	#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT 0
	#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT)
	#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT 16
	#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT)
	#define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */
	#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
	#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
	#define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */
	#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0
	#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
	#define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */
	#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0
	#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
	#define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */
	#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT 0
	#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK I40E_MASK(0xFFFF, I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT)
	#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT 17
	#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT)
	#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT 18
	#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT)
	#define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */
	#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT 0
	#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK I40E_MASK(0x1, I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT)
	#define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX 15
	#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0
	#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
	#define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX 15
	#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0
	#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
	#define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 / / Reset: CORER */
	#define I40E_GLPE_PFCQEDROPCNT_MAX_INDEX 15
	#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT 0
	#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT)
	#define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */
	#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT 0
	#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT)
	#define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */
	#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT 0
	#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT)
	#define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */
	#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT 0
	#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT)
	#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT 26
	#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT)
	#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT 27
	#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT)
	#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT 28
	#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT)
	#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT 29
	#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT)
	#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT 30
	#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT)
	#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT 31
	#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT)
	#define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */
	#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT 0
	#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT)
	#define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */
	#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT 0
	#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT)
	#define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */
	#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT 0
	#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT)
	#define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX 31
	#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0
	#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
	#define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX 31
	#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0
	#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
	#define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 / / Reset: CORER */
	#define I40E_GLPE_VFCQEDROPCNT_MAX_INDEX 31
	#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT 0
	#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT)
	#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31
	#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
	#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
	#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
	#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
	#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
	#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
	#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
	#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
	#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
	#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
	#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31
	#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0
	#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
	#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1
	#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
	#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2
	#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
	#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3
	#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
	#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
	#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
	#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31
	#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0
	#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
	#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31
	#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
	#define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
	#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0
	#define I40E_PFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
	#define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
	#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
	#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
	#define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
	#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0
	#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
	#define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */
	#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
	#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
	#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
	#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
	#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16
	#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
	#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
	#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
	#define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */
	#define I40E_PFPE_CQACK_PECQID_SHIFT 0
	#define I40E_PFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQACK_PECQID_SHIFT)
	#define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */
	#define I40E_PFPE_CQARM_PECQID_SHIFT 0
	#define I40E_PFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQARM_PECQID_SHIFT)
	#define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */
	#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0
	#define I40E_PFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPDB_WQHEAD_SHIFT)
	#define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */
	#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
	#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
	#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
	#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
	#define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */
	#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0
	#define I40E_PFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
	#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
	#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
	#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */
	#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
	#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
	#define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */
	#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
	#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
	#define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */
	#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0
	#define I40E_PFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
	#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
	#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
	#define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */
	#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
	#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
	#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */
	#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
	#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
	#define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */
	#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
	#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
	#define I40E_PFPE_UDACTRL 0x00008700 /* Reset: PFR */
	#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0
	#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
	#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1
	#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
	#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2
	#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
	#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3
	#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
	#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
	#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
	#define I40E_PFPE_UDAUCFBQPN 0x00008780 /* Reset: PFR */
	#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0
	#define I40E_PFPE_UDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
	#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31
	#define I40E_PFPE_UDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
	#define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */
	#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0
	#define I40E_PFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
	#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
	#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
	#define I40E_PRTDCB_RLPMC 0x0001F140 /* Reset: PE_CORER */
	#define I40E_PRTDCB_RLPMC_TC2PFC_SHIFT 0
	#define I40E_PRTDCB_RLPMC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RLPMC_TC2PFC_SHIFT)
	#define I40E_PRTDCB_TCMSTC_RLPM(_i) (0x0001F040 + ((_i) * 32)) /* _i=0...7 / / Reset: PE_CORER */
	#define I40E_PRTDCB_TCMSTC_RLPM_MAX_INDEX 7
	#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT 0
	#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT)
	#define I40E_PRTDCB_TCPMC_RLPM 0x0001F1A0 /* Reset: PE_CORER */
	#define I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT 0
	#define I40E_PRTDCB_TCPMC_RLPM_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT)
	#define I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT 13
	#define I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT)
	#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT 30
	#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT)
	#define I40E_PRTE_RUPM_TCCNTR03 0x0000DAE0 /* Reset: PE_CORER */
	#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT 0
	#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT)
	#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT 8
	#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT)
	#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT 16
	#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT)
	#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT 24
	#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_CNTR 0x0000DB20 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT 0
	#define I40E_PRTPE_RUPM_CNTR_COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_CTL 0x0000DA40 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_CTL_LLTC_SHIFT 13
	#define I40E_PRTPE_RUPM_CTL_LLTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CTL_LLTC_SHIFT)
	#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT 30
	#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT)
	#define I40E_PRTPE_RUPM_PFCCTL 0x0000DA60 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT 0
	#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT)
	#define I40E_PRTPE_RUPM_PFCPC 0x0000DA80 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT 0
	#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT)
	#define I40E_PRTPE_RUPM_PFCTCC 0x0000DAA0 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT 0
	#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT)
	#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT 16
	#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT)
	#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT 31
	#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT)
	#define I40E_PRTPE_RUPM_PTCTCCNTR47 0x0000DB60 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT 0
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT 8
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT 16
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT 24
	#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTXTCCNTR03 0x0000DB40 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT 0
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT 8
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT 16
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT 24
	#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_TCCNTR47 0x0000DB00 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT 0
	#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT 8
	#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT 16
	#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT 24
	#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT)
	#define I40E_PRTPE_RUPM_THRES 0x0000DA20 /* Reset: PE_CORER */
	#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT 0
	#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT)
	#define I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT 8
	#define I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT)
	#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT 16
	#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT)
	#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_AEQALLOC_MAX_INDEX 127
	#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0
	#define I40E_VFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
	#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127
	#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
	#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
	#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CCQPLOW_MAX_INDEX 127
	#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0
	#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
	#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127
	#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
	#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
	#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
	#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
	#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16
	#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
	#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
	#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
	#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CQACK_MAX_INDEX 127
	#define I40E_VFPE_CQACK_PECQID_SHIFT 0
	#define I40E_VFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK_PECQID_SHIFT)
	#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CQARM_MAX_INDEX 127
	#define I40E_VFPE_CQARM_PECQID_SHIFT 0
	#define I40E_VFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM_PECQID_SHIFT)
	#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CQPDB_MAX_INDEX 127
	#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0
	#define I40E_VFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB_WQHEAD_SHIFT)
	#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127
	#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
	#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
	#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
	#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
	#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_CQPTAIL_MAX_INDEX 127
	#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0
	#define I40E_VFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
	#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
	#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
	#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127
	#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0
	#define I40E_VFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
	#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
	#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
	#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
	#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
	#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
	#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127
	#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
	#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
	#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127
	#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
	#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
	#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 / / Reset: VFR */
	#define I40E_VFPE_WQEALLOC_MAX_INDEX 127
	#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0
	#define I40E_VFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
	#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
	#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
	#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
	#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
	#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
	#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
	#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
	#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
	#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15
	#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
	#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
	#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
	#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
	#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
	#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
	#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
	#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
	#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
	#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
	#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
	#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
	#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
	#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
	#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15
	#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
	#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
	#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
	#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
	#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
	#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
	#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
	#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
	#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
	#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
	#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
	#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
	#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
	#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
	#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
	#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
	#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
	#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
	#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
	#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
	#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
	#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
	#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
	#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
	#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
	#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
	#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
	#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
	#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
	#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
	#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
	#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
	#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
	#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
	#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
	#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
	#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
	#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
	#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
	#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
	#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
	#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
	#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
	#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15
	#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0
	#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
	#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15
	#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0
	#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
	#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15
	#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0
	#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
	#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15
	#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0
	#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
	#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15
	#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
	#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
	#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15
	#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
	#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
	#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15
	#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
	#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
	#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15
	#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
	#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
	#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15
	#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
	#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
	#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15
	#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
	#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
	#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
	#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
	#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
	#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
	#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15
	#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
	#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
	#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 / / Reset: PE_CORER */
	#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15
	#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
	#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
	#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */
	#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0
	#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
	#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */
	#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0
	#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
	#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */
	#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0
	#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
	#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */
	#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0
	#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
	#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */
	#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0
	#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
	#define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */
	#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0
	#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
	#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0
	#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
	#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0
	#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
	#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0
	#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
	#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0
	#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
	#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0
	#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
	#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0
	#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
	#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0
	#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
	#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0
	#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
	#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0
	#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
	#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0
	#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
	#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */
	#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0
	#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
	#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0
	#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
	#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0
	#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
	#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0
	#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
	#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */
	#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0
	#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
	#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */
	#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0
	#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
	#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
	#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
	#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
	#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
	#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
	#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
	#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31
	#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
	#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
	#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
	#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
	#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
	#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
	#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
	#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
	#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
	#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
	#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
	#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
	#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
	#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
	#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31
	#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
	#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
	#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
	#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
	#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
	#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
	#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
	#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
	#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
	#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
	#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
	#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
	#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
	#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
	#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
	#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
	#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
	#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
	#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
	#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
	#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
	#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
	#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
	#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
	#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
	#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
	#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
	#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
	#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
	#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
	#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
	#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
	#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
	#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
	#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
	#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
	#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
	#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
	#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
	#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
	#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
	#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
	#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
	#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31
	#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0
	#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
	#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31
	#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0
	#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
	#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31
	#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0
	#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
	#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31
	#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0
	#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
	#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31
	#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
	#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
	#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31
	#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
	#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
	#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31
	#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
	#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
	#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31
	#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
	#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
	#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31
	#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
	#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
	#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31
	#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
	#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
	#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
	#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
	#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
	#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
	#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31
	#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
	#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
	#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 / / Reset: PE_CORER */
	#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
	#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
	#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
	#define I40E_GLGEN_PME_TO 0x000B81BC /* Reset: POR */
	#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT 0
	#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK I40E_MASK(0x1, I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT)
	#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 / / Reset: CORER */
	#define I40E_GLQF_APBVT_MAX_INDEX 2047
	#define I40E_GLQF_APBVT_APBVT_SHIFT 0
	#define I40E_GLQF_APBVT_APBVT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_APBVT_APBVT_SHIFT)
	#define I40E_GLQF_FD_PCTYPES(_i) (0x00268000 + ((_i) * 4)) /* _i=0...63 / / Reset: POR */
	#define I40E_GLQF_FD_PCTYPES_MAX_INDEX 63
	#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0
	#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT)
	#define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 / / Reset: CORER */
	#define I40E_GLQF_FDEVICTENA_MAX_INDEX 1
	#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0
	#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT)
	#define I40E_GLQF_FDEVICTFLAG 0x00270280 /* Reset: CORER */
	#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT 0
	#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT)
	#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT 8
	#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT)
	#define I40E_PFQF_CTL_2 0x00270300 /* Reset: CORER */
	#define I40E_PFQF_CTL_2_PEHSIZE_SHIFT 0
	#define I40E_PFQF_CTL_2_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEHSIZE_SHIFT)
	#define I40E_PFQF_CTL_2_PEDSIZE_SHIFT 5
	#define I40E_PFQF_CTL_2_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEDSIZE_SHIFT)
	/* Redefined for X722 family */
	#define I40E_X722_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 / / Reset: CORER */
	#define I40E_X722_PFQF_HLUT_MAX_INDEX 127
	#define I40E_X722_PFQF_HLUT_LUT0_SHIFT 0
	#define I40E_X722_PFQF_HLUT_LUT0_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT0_SHIFT)
	#define I40E_X722_PFQF_HLUT_LUT1_SHIFT 8
	#define I40E_X722_PFQF_HLUT_LUT1_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT1_SHIFT)
	#define I40E_X722_PFQF_HLUT_LUT2_SHIFT 16
	#define I40E_X722_PFQF_HLUT_LUT2_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT2_SHIFT)
	#define I40E_X722_PFQF_HLUT_LUT3_SHIFT 24
	#define I40E_X722_PFQF_HLUT_LUT3_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT3_SHIFT)
	#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 / / Reset: CORER */
	#define I40E_PFQF_HREGION_MAX_INDEX 7
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
	#define I40E_PFQF_HREGION_REGION_0_SHIFT 1
	#define I40E_PFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
	#define I40E_PFQF_HREGION_REGION_1_SHIFT 5
	#define I40E_PFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
	#define I40E_PFQF_HREGION_REGION_2_SHIFT 9
	#define I40E_PFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
	#define I40E_PFQF_HREGION_REGION_3_SHIFT 13
	#define I40E_PFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
	#define I40E_PFQF_HREGION_REGION_4_SHIFT 17
	#define I40E_PFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
	#define I40E_PFQF_HREGION_REGION_5_SHIFT 21
	#define I40E_PFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
	#define I40E_PFQF_HREGION_REGION_6_SHIFT 25
	#define I40E_PFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT)
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
	#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
	#define I40E_PFQF_HREGION_REGION_7_SHIFT 29
	#define I40E_PFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT)
	#define I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT 8
	#define I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT)
	#define I40E_VSIQF_HKEY(_i, _VSI) (0x002A0000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...12, _VSI=0...383 / / Reset: CORER */
	#define I40E_VSIQF_HKEY_MAX_INDEX 12
	#define I40E_VSIQF_HKEY_KEY_0_SHIFT 0
	#define I40E_VSIQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_0_SHIFT)
	#define I40E_VSIQF_HKEY_KEY_1_SHIFT 8
	#define I40E_VSIQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_1_SHIFT)
	#define I40E_VSIQF_HKEY_KEY_2_SHIFT 16
	#define I40E_VSIQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_2_SHIFT)
	#define I40E_VSIQF_HKEY_KEY_3_SHIFT 24
	#define I40E_VSIQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_3_SHIFT)
	#define I40E_VSIQF_HLUT(_i, _VSI) (0x00220000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...15, _VSI=0...383 / / Reset: CORER */
	#define I40E_VSIQF_HLUT_MAX_INDEX 15
	#define I40E_VSIQF_HLUT_LUT0_SHIFT 0
	#define I40E_VSIQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT0_SHIFT)
	#define I40E_VSIQF_HLUT_LUT1_SHIFT 8
	#define I40E_VSIQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT1_SHIFT)
	#define I40E_VSIQF_HLUT_LUT2_SHIFT 16
	#define I40E_VSIQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT2_SHIFT)
	#define I40E_VSIQF_HLUT_LUT3_SHIFT 24
	#define I40E_VSIQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT3_SHIFT)
	#define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */
	#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT 0
	#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT)
	#define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */
	#define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0
	#define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT)
	#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30
	#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
	#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
	#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
	#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
	#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
	#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
	#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
	#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
	#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
	#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
	#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
	#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
	#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
	#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
	#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
	#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
	#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
	#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
	#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
	#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
	#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
	#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
	#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
	#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)
	#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
	#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
	#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)
	#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
	#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
	#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
	#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
	#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
	#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
	#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
	#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
	#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
	#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
	#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
	#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
	#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
	#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */
	#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
	#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
	#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
	#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
	#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */
	#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
	#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
	#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */
	#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
	#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
	#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */
	#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
	#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
	#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
	#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
	#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
	#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
	#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)

	#endif /* X722_SUPPORT */
	#endif /* _I40E_REGISTER_H_ */			#endif /* _I40E_REGISTER_H_ */