Differential D45176 Diff 138647 sys/arm64/include/armreg.h

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sys/arm64/include/armreg.h

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	#define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK)			#define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK)
	#define ICC_SGI1R_EL1_IRM (0x1UL << 40)			#define ICC_SGI1R_EL1_IRM (0x1UL << 40)

	/* ICC_SRE_EL1 */			/* ICC_SRE_EL1 */
	#define ICC_SRE_EL1_SRE (1U << 0)			#define ICC_SRE_EL1_SRE (1U << 0)

	/* ID_AA64AFR0_EL1 */			/* ID_AA64AFR0_EL1 */
	#define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1)			#define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1)
				#define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1)
	#define ID_AA64AFR0_EL1_op0 3			#define ID_AA64AFR0_EL1_op0 3
	#define ID_AA64AFR0_EL1_op1 0			#define ID_AA64AFR0_EL1_op1 0
	#define ID_AA64AFR0_EL1_CRn 0			#define ID_AA64AFR0_EL1_CRn 0
	#define ID_AA64AFR0_EL1_CRm 5			#define ID_AA64AFR0_EL1_CRm 5
	#define ID_AA64AFR0_EL1_op2 4			#define ID_AA64AFR0_EL1_op2 4

	/* ID_AA64AFR1_EL1 */			/* ID_AA64AFR1_EL1 */
	#define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1)			#define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1)
				#define ID_AA64AFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR1_EL1)
	#define ID_AA64AFR1_EL1_op0 3			#define ID_AA64AFR1_EL1_op0 3
	#define ID_AA64AFR1_EL1_op1 0			#define ID_AA64AFR1_EL1_op1 0
	#define ID_AA64AFR1_EL1_CRn 0			#define ID_AA64AFR1_EL1_CRn 0
	#define ID_AA64AFR1_EL1_CRm 5			#define ID_AA64AFR1_EL1_CRm 5
	#define ID_AA64AFR1_EL1_op2 5			#define ID_AA64AFR1_EL1_op2 5

	/* ID_AA64DFR0_EL1 */			/* ID_AA64DFR0_EL1 */
	#define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1)			#define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1)
				#define ID_AA64DFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR0_EL1)
	#define ID_AA64DFR0_EL1_op0 3			#define ID_AA64DFR0_EL1_op0 3
	#define ID_AA64DFR0_EL1_op1 0			#define ID_AA64DFR0_EL1_op1 0
	#define ID_AA64DFR0_EL1_CRn 0			#define ID_AA64DFR0_EL1_CRn 0
	#define ID_AA64DFR0_EL1_CRm 5			#define ID_AA64DFR0_EL1_CRm 5
	#define ID_AA64DFR0_EL1_op2 0			#define ID_AA64DFR0_EL1_op2 0
	#define ID_AA64DFR0_DebugVer_SHIFT 0			#define ID_AA64DFR0_DebugVer_SHIFT 0
	#define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)			#define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
	#define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK)			#define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK)
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	#define ID_AA64DFR0_HPMN0_SHIFT 60			#define ID_AA64DFR0_HPMN0_SHIFT 60
	#define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT)			#define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT)
	#define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK)			#define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK)
	#define ID_AA64DFR0_HPMN0_CONSTR (UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT)			#define ID_AA64DFR0_HPMN0_CONSTR (UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT)
	#define ID_AA64DFR0_HPMN0_DEFINED (UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT)			#define ID_AA64DFR0_HPMN0_DEFINED (UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT)

	/* ID_AA64DFR1_EL1 */			/* ID_AA64DFR1_EL1 */
	#define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1)			#define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1)
				#define ID_AA64DFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR1_EL1)
	#define ID_AA64DFR1_EL1_op0 3			#define ID_AA64DFR1_EL1_op0 3
	#define ID_AA64DFR1_EL1_op1 0			#define ID_AA64DFR1_EL1_op1 0
	#define ID_AA64DFR1_EL1_CRn 0			#define ID_AA64DFR1_EL1_CRn 0
	#define ID_AA64DFR1_EL1_CRm 5			#define ID_AA64DFR1_EL1_CRm 5
	#define ID_AA64DFR1_EL1_op2 1			#define ID_AA64DFR1_EL1_op2 1

	/* ID_AA64ISAR0_EL1 */			/* ID_AA64ISAR0_EL1 */
	#define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1)			#define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1)
				#define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1)
	#define ID_AA64ISAR0_EL1_op0 3			#define ID_AA64ISAR0_EL1_op0 3
	#define ID_AA64ISAR0_EL1_op1 0			#define ID_AA64ISAR0_EL1_op1 0
	#define ID_AA64ISAR0_EL1_CRn 0			#define ID_AA64ISAR0_EL1_CRn 0
	#define ID_AA64ISAR0_EL1_CRm 6			#define ID_AA64ISAR0_EL1_CRm 6
	#define ID_AA64ISAR0_EL1_op2 0			#define ID_AA64ISAR0_EL1_op2 0
	#define ID_AA64ISAR0_AES_SHIFT 4			#define ID_AA64ISAR0_AES_SHIFT 4
	#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)			#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
	#define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK)			#define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK)
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	#define ID_AA64ISAR0_RNDR_SHIFT 60			#define ID_AA64ISAR0_RNDR_SHIFT 60
	#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)			#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
	#define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK)			#define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK)
	#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)			#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
	#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)			#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)

	/* ID_AA64ISAR1_EL1 */			/* ID_AA64ISAR1_EL1 */
	#define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1)			#define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1)
				#define ID_AA64ISAR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1)
	#define ID_AA64ISAR1_EL1_op0 3			#define ID_AA64ISAR1_EL1_op0 3
	#define ID_AA64ISAR1_EL1_op1 0			#define ID_AA64ISAR1_EL1_op1 0
	#define ID_AA64ISAR1_EL1_CRn 0			#define ID_AA64ISAR1_EL1_CRn 0
	#define ID_AA64ISAR1_EL1_CRm 6			#define ID_AA64ISAR1_EL1_CRm 6
	#define ID_AA64ISAR1_EL1_op2 1			#define ID_AA64ISAR1_EL1_op2 1
	#define ID_AA64ISAR1_DPB_SHIFT 0			#define ID_AA64ISAR1_DPB_SHIFT 0
	#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)			#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
	#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK)			#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK)
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	#define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK)			#define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK)
	#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT)			#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT)
	#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT)			#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT)
	#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT)			#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT)
	#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT)			#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT)

	/* ID_AA64ISAR2_EL1 */			/* ID_AA64ISAR2_EL1 */
	#define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1)			#define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1)
				#define ID_AA64ISAR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1)
	#define ID_AA64ISAR2_EL1_op0 3			#define ID_AA64ISAR2_EL1_op0 3
	#define ID_AA64ISAR2_EL1_op1 0			#define ID_AA64ISAR2_EL1_op1 0
	#define ID_AA64ISAR2_EL1_CRn 0			#define ID_AA64ISAR2_EL1_CRn 0
	#define ID_AA64ISAR2_EL1_CRm 6			#define ID_AA64ISAR2_EL1_CRm 6
	#define ID_AA64ISAR2_EL1_op2 2			#define ID_AA64ISAR2_EL1_op2 2
	#define ID_AA64ISAR2_WFxT_SHIFT 0			#define ID_AA64ISAR2_WFxT_SHIFT 0
	#define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)			#define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)
	#define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK)			#define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK)
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	#define ID_AA64ISAR2_PAC_frac_SHIFT 28			#define ID_AA64ISAR2_PAC_frac_SHIFT 28
	#define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)			#define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)
	#define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK)			#define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK)
	#define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)			#define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)
	#define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)			#define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)

	/* ID_AA64MMFR0_EL1 */			/* ID_AA64MMFR0_EL1 */
	#define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1)			#define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1)
				#define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1)
	#define ID_AA64MMFR0_EL1_op0 3			#define ID_AA64MMFR0_EL1_op0 3
	#define ID_AA64MMFR0_EL1_op1 0			#define ID_AA64MMFR0_EL1_op1 0
	#define ID_AA64MMFR0_EL1_CRn 0			#define ID_AA64MMFR0_EL1_CRn 0
	#define ID_AA64MMFR0_EL1_CRm 7			#define ID_AA64MMFR0_EL1_CRm 7
	#define ID_AA64MMFR0_EL1_op2 0			#define ID_AA64MMFR0_EL1_op2 0
	#define ID_AA64MMFR0_PARange_SHIFT 0			#define ID_AA64MMFR0_PARange_SHIFT 0
	#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)			#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
	#define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK)			#define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK)
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	#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)			#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)
	#define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK)			#define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK)
	#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)			#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)
	#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)			#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)
	#define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)			#define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)

	/* ID_AA64MMFR1_EL1 */			/* ID_AA64MMFR1_EL1 */
	#define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1)			#define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1)
				#define ID_AA64MMFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1)
	#define ID_AA64MMFR1_EL1_op0 3			#define ID_AA64MMFR1_EL1_op0 3
	#define ID_AA64MMFR1_EL1_op1 0			#define ID_AA64MMFR1_EL1_op1 0
	#define ID_AA64MMFR1_EL1_CRn 0			#define ID_AA64MMFR1_EL1_CRn 0
	#define ID_AA64MMFR1_EL1_CRm 7			#define ID_AA64MMFR1_EL1_CRm 7
	#define ID_AA64MMFR1_EL1_op2 1			#define ID_AA64MMFR1_EL1_op2 1
	#define ID_AA64MMFR1_HAFDBS_SHIFT 0			#define ID_AA64MMFR1_HAFDBS_SHIFT 0
	#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)			#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
	#define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)			#define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
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	#define ID_AA64MMFR1_CMOVW_SHIFT 56			#define ID_AA64MMFR1_CMOVW_SHIFT 56
	#define ID_AA64MMFR1_CMOVW_MASK (UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT)			#define ID_AA64MMFR1_CMOVW_MASK (UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT)
	#define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK)			#define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK)
	#define ID_AA64MMFR1_CMOVW_NONE (UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT)			#define ID_AA64MMFR1_CMOVW_NONE (UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT)
	#define ID_AA64MMFR1_CMOVW_IMPL (UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT)			#define ID_AA64MMFR1_CMOVW_IMPL (UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT)

	/* ID_AA64MMFR2_EL1 */			/* ID_AA64MMFR2_EL1 */
	#define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1)			#define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1)
				#define ID_AA64MMFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1)
	#define ID_AA64MMFR2_EL1_op0 3			#define ID_AA64MMFR2_EL1_op0 3
	#define ID_AA64MMFR2_EL1_op1 0			#define ID_AA64MMFR2_EL1_op1 0
	#define ID_AA64MMFR2_EL1_CRn 0			#define ID_AA64MMFR2_EL1_CRn 0
	#define ID_AA64MMFR2_EL1_CRm 7			#define ID_AA64MMFR2_EL1_CRm 7
	#define ID_AA64MMFR2_EL1_op2 2			#define ID_AA64MMFR2_EL1_op2 2
	#define ID_AA64MMFR2_CnP_SHIFT 0			#define ID_AA64MMFR2_CnP_SHIFT 0
	#define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)			#define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
	#define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK)			#define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK)
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	#define ID_AA64MMFR2_E0PD_SHIFT 60			#define ID_AA64MMFR2_E0PD_SHIFT 60
	#define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)			#define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
	#define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK)			#define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK)
	#define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)			#define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
	#define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)			#define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)

	/* ID_AA64MMFR3_EL1 */			/* ID_AA64MMFR3_EL1 */
	#define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1)			#define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1)
				#define ID_AA64MMFR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1)
	#define ID_AA64MMFR3_EL1_op0 3			#define ID_AA64MMFR3_EL1_op0 3
	#define ID_AA64MMFR3_EL1_op1 0			#define ID_AA64MMFR3_EL1_op1 0
	#define ID_AA64MMFR3_EL1_CRn 0			#define ID_AA64MMFR3_EL1_CRn 0
	#define ID_AA64MMFR3_EL1_CRm 7			#define ID_AA64MMFR3_EL1_CRm 7
	#define ID_AA64MMFR3_EL1_op2 3			#define ID_AA64MMFR3_EL1_op2 3
	#define ID_AA64MMFR3_TCRX_SHIFT 0			#define ID_AA64MMFR3_TCRX_SHIFT 0
	#define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT)			#define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT)
	#define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK)			#define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK)
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	#define ID_AA64MMFR3_Spec_FPACC_SHIFT 60			#define ID_AA64MMFR3_Spec_FPACC_SHIFT 60
	#define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT)			#define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
	#define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK)			#define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK)
	#define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)			#define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
	#define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)			#define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)

	/* ID_AA64MMFR4_EL1 */			/* ID_AA64MMFR4_EL1 */
	#define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1)			#define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1)
				#define ID_AA64MMFR4_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1)
	#define ID_AA64MMFR4_EL1_op0 3			#define ID_AA64MMFR4_EL1_op0 3
	#define ID_AA64MMFR4_EL1_op1 0			#define ID_AA64MMFR4_EL1_op1 0
	#define ID_AA64MMFR4_EL1_CRn 0			#define ID_AA64MMFR4_EL1_CRn 0
	#define ID_AA64MMFR4_EL1_CRm 7			#define ID_AA64MMFR4_EL1_CRm 7
	#define ID_AA64MMFR4_EL1_op2 4			#define ID_AA64MMFR4_EL1_op2 4

	/* ID_AA64PFR0_EL1 */			/* ID_AA64PFR0_EL1 */
	#define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1)			#define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1)
				#define ID_AA64PFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR0_EL1)
	#define ID_AA64PFR0_EL1_op0 3			#define ID_AA64PFR0_EL1_op0 3
	#define ID_AA64PFR0_EL1_op1 0			#define ID_AA64PFR0_EL1_op1 0
	#define ID_AA64PFR0_EL1_CRn 0			#define ID_AA64PFR0_EL1_CRn 0
	#define ID_AA64PFR0_EL1_CRm 4			#define ID_AA64PFR0_EL1_CRm 4
	#define ID_AA64PFR0_EL1_op2 0			#define ID_AA64PFR0_EL1_op2 0
	#define ID_AA64PFR0_EL0_SHIFT 0			#define ID_AA64PFR0_EL0_SHIFT 0
	#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)			#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
	#define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK)			#define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK)
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	#define ID_AA64PFR0_CSV3_SHIFT 60			#define ID_AA64PFR0_CSV3_SHIFT 60
	#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)			#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
	#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK)			#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK)
	#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)			#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
	#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)			#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)

	/* ID_AA64PFR1_EL1 */			/* ID_AA64PFR1_EL1 */
	#define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1)			#define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1)
				#define ID_AA64PFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR1_EL1)
	#define ID_AA64PFR1_EL1_op0 3			#define ID_AA64PFR1_EL1_op0 3
	#define ID_AA64PFR1_EL1_op1 0			#define ID_AA64PFR1_EL1_op1 0
	#define ID_AA64PFR1_EL1_CRn 0			#define ID_AA64PFR1_EL1_CRn 0
	#define ID_AA64PFR1_EL1_CRm 4			#define ID_AA64PFR1_EL1_CRm 4
	#define ID_AA64PFR1_EL1_op2 1			#define ID_AA64PFR1_EL1_op2 1
	#define ID_AA64PFR1_BT_SHIFT 0			#define ID_AA64PFR1_BT_SHIFT 0
	#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT)			#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
	#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK)			#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK)
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	#define ID_AA64PFR1_NMI_SHIFT 36			#define ID_AA64PFR1_NMI_SHIFT 36
	#define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT)			#define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT)
	#define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK)			#define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK)
	#define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT)			#define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT)
	#define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT)			#define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT)

	/* ID_AA64PFR2_EL1 */			/* ID_AA64PFR2_EL1 */
	#define ID_AA64PFR2_EL1 MRS_REG(ID_AA64PFR2_EL1)			#define ID_AA64PFR2_EL1 MRS_REG(ID_AA64PFR2_EL1)
				#define ID_AA64PFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR2_EL1)
	#define ID_AA64PFR2_EL1_op0 3			#define ID_AA64PFR2_EL1_op0 3
	#define ID_AA64PFR2_EL1_op1 0			#define ID_AA64PFR2_EL1_op1 0
	#define ID_AA64PFR2_EL1_CRn 0			#define ID_AA64PFR2_EL1_CRn 0
	#define ID_AA64PFR2_EL1_CRm 4			#define ID_AA64PFR2_EL1_CRm 4
	#define ID_AA64PFR2_EL1_op2 2			#define ID_AA64PFR2_EL1_op2 2

	/* ID_AA64ZFR0_EL1 */			/* ID_AA64ZFR0_EL1 */
	#define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1)			#define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1)
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