Differential D27889 Diff 130880 sys/arm/ti/clk/ti_clk_clkctrl.c

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sys/arm/ti/clk/ti_clk_clkctrl.c

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
#else		#else
#define DPRINTF(dev, msg...)		#define DPRINTF(dev, msg...)
#endif		#endif

/*		/*
* clknode for clkctrl, implements gate and mux (for gpioc)		* clknode for clkctrl, implements gate and mux (for gpioc)
*/		*/

#define GPIO_X_GDBCLK_MASK 0x00040000
#define IDLEST_MASK 0x00030000		#define IDLEST_MASK 0x00030000
#define MODULEMODE_MASK 0x00000003		#define MODULEMODE_MASK 0x00000003

#define GPIOX_GDBCLK_ENABLE 0x00040000
#define GPIOX_GDBCLK_DISABLE 0x00000000
#define IDLEST_FUNC 0x00000000		#define IDLEST_FUNC 0x00000000
#define IDLEST_TRANS 0x00010000		#define IDLEST_TRANS 0x00010000
#define IDLEST_IDLE 0x00020000		#define IDLEST_IDLE 0x00020000
#define IDLEST_DISABLE 0x00030000		#define IDLEST_DISABLE 0x00030000

#define MODULEMODE_DISABLE 0x0		#define MODULEMODE_DISABLE 0x0
#define MODULEMODE_ENABLE 0x2		#define MODULEMODE_ENABLE 0x2

struct ti_clkctrl_clknode_sc {		struct ti_clkctrl_clknode_sc {
device_t dev;		device_t dev;
bool gdbclk;
/* omap4-cm range.host + ti,clkctrl reg[0] */		/* omap4-cm range.host + ti,clkctrl reg[0] */
uint32_t register_offset;		uint32_t register_offset;
};		};

#define WRITE4(_clk, off, val) \		#define WRITE4(_clk, off, val) \
CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)		CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
#define READ4(_clk, off, val) \		#define READ4(_clk, off, val) \
CLKDEV_READ_4(clknode_get_device(_clk), off, val)		CLKDEV_READ_4(clknode_get_device(_clk), off, val)
Show All 10 Lines	ti_clkctrl_init(struct clknode *clk, device_t dev)
sc = clknode_get_softc(clk);		sc = clknode_get_softc(clk);
sc->dev = dev;		sc->dev = dev;

clknode_init_parent_idx(clk, 0);		clknode_init_parent_idx(clk, 0);
return (0);		return (0);
}		}

static int		static int
ti_clkctrl_set_gdbclk_gate(struct clknode *clk, bool enable)
{
struct ti_clkctrl_clknode_sc *sc;
uint32_t val, gpio_x_gdbclk;
uint32_t timeout = 100;

sc = clknode_get_softc(clk);

READ4(clk, sc->register_offset, &val);
DPRINTF(sc->dev, "val(%x) & (%x \| %x = %x)\n",
val, GPIO_X_GDBCLK_MASK, MODULEMODE_MASK,
GPIO_X_GDBCLK_MASK \| MODULEMODE_MASK);

if (enable) {
val = val & MODULEMODE_MASK;
val \|= GPIOX_GDBCLK_ENABLE;
} else {
val = val & MODULEMODE_MASK;
val \|= GPIOX_GDBCLK_DISABLE;
}

DPRINTF(sc->dev, "val %x\n", val);
WRITE4(clk, sc->register_offset, val);

/* Wait */
while (timeout) {
READ4(clk, sc->register_offset, &val);
gpio_x_gdbclk = val & GPIO_X_GDBCLK_MASK;
if (enable && (gpio_x_gdbclk == GPIOX_GDBCLK_ENABLE))
break;
else if (!enable && (gpio_x_gdbclk == GPIOX_GDBCLK_DISABLE))
break;
DELAY(10);
timeout--;
}
if (timeout == 0) {
device_printf(sc->dev, "ti_clkctrl_set_gdbclk_gate: Timeout\n");
return (1);
}

return (0);
}

static int
ti_clkctrl_set_gate(struct clknode *clk, bool enable)		ti_clkctrl_set_gate(struct clknode *clk, bool enable)
{		{
struct ti_clkctrl_clknode_sc *sc;		struct ti_clkctrl_clknode_sc *sc;
uint32_t val, idlest, module;		uint32_t val, idlest, module;
uint32_t timeout=100;		uint32_t timeout=100;
int err;

sc = clknode_get_softc(clk);		sc = clknode_get_softc(clk);

if (sc->gdbclk) {		DEVICE_LOCK(clk);
err = ti_clkctrl_set_gdbclk_gate(clk, enable);
return (err);
}

READ4(clk, sc->register_offset, &val);		READ4(clk, sc->register_offset, &val);

if (enable)		if (enable)
WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);		WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);
else		else
WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);		WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);

while (timeout) {		while (timeout) {
READ4(clk, sc->register_offset, &val);		READ4(clk, sc->register_offset, &val);
idlest = val & IDLEST_MASK;		idlest = val & IDLEST_MASK;
module = val & MODULEMODE_MASK;		module = val & MODULEMODE_MASK;
if (enable &&		if (enable &&
(idlest == IDLEST_FUNC \|\| idlest == IDLEST_TRANS) &&		(idlest == IDLEST_FUNC \|\| idlest == IDLEST_TRANS) &&
module == MODULEMODE_ENABLE)		module == MODULEMODE_ENABLE)
break;		break;
else if (!enable &&		else if (!enable &&
idlest == IDLEST_DISABLE &&		idlest == IDLEST_DISABLE &&
module == MODULEMODE_DISABLE)		module == MODULEMODE_DISABLE)
break;		break;
DELAY(10);		DELAY(10);
timeout--;		timeout--;
}		}

		DEVICE_UNLOCK(clk);
if (timeout == 0) {		if (timeout == 0) {
device_printf(sc->dev, "ti_clkctrl_set_gate: Timeout\n");		DPRINTF(sc->dev, "ti_clkctrl_set_gate: Timeout\n");
return (1);		return (1);
}		}

return (0);		return (0);
}		}

static clknode_method_t ti_clkctrl_clknode_methods[] = {		static clknode_method_t ti_clkctrl_clknode_methods[] = {
/* Device interface */		/* Device interface */
Show All 17 Lines	clk = clknode_create(clkdom, &ti_clkctrl_clknode_class,
&clkdef->clkdef);		&clkdef->clkdef);

if (clk == NULL) {		if (clk == NULL) {
return (1);		return (1);
}		}

sc = clknode_get_softc(clk);		sc = clknode_get_softc(clk);
sc->register_offset = clkdef->register_offset;		sc->register_offset = clkdef->register_offset;
sc->gdbclk = clkdef->gdbclk;

if (clknode_register(clkdom, clk) == NULL) {		if (clknode_register(clkdom, clk) == NULL) {
return (2);		return (2);
}		}
return (0);		return (0);
}		}