Differential D5752 Diff 14954 head/sys/arm/allwinner/a10_dmac.c

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head/sys/arm/allwinner/a10_dmac.c

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#include <sys/module.h>		#include <sys/module.h>

#include <machine/bus.h>		#include <machine/bus.h>

#include <dev/ofw/ofw_bus.h>		#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>		#include <dev/ofw/ofw_bus_subr.h>

#include <arm/allwinner/a10_dmac.h>		#include <arm/allwinner/a10_dmac.h>
#include <arm/allwinner/a10_clk.h>		#include <dev/extres/clk/clk.h>

#include "sunxi_dma_if.h"		#include "sunxi_dma_if.h"

#define NDMA_CHANNELS 8		#define NDMA_CHANNELS 8
#define DDMA_CHANNELS 8		#define DDMA_CHANNELS 8

enum a10dmac_type {		enum a10dmac_type {
CH_NDMA,		CH_NDMA,
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines	a10dmac_probe(device_t dev)
return (BUS_PROBE_DEFAULT);		return (BUS_PROBE_DEFAULT);
}		}

static int		static int
a10dmac_attach(device_t dev)		a10dmac_attach(device_t dev)
{		{
struct a10dmac_softc *sc;		struct a10dmac_softc *sc;
unsigned int index;		unsigned int index;
		clk_t clk;
int error;		int error;

sc = device_get_softc(dev);		sc = device_get_softc(dev);

if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) {		if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) {
device_printf(dev, "cannot allocate resources for device\n");		device_printf(dev, "cannot allocate resources for device\n");
return (ENXIO);		return (ENXIO);
}		}

mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN);		mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN);

/* Activate DMA controller clock */		/* Activate DMA controller clock */
a10_clk_dmac_activate();		error = clk_get_by_ofw_index(dev, 0, &clk);
		if (error != 0) {
		device_printf(dev, "cannot get clock\n");
		return (error);
		}
		error = clk_enable(clk);
		if (error != 0) {
		device_printf(dev, "cannot enable clock\n");
		return (error);
		}

/* Disable all interrupts and clear pending status */		/* Disable all interrupts and clear pending status */
DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);		DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);
DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);		DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);

/* Initialize channels */		/* Initialize channels */
for (index = 0; index < NDMA_CHANNELS; index++) {		for (index = 0; index < NDMA_CHANNELS; index++) {
sc->sc_ndma_channels[index].ch_sc = sc;		sc->sc_ndma_channels[index].ch_sc = sc;
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