Differential D5805 Diff 14856 head/sys/arm/ti/aintc.c

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head/sys/arm/ti/aintc.c

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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF		* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.		* SUCH DAMAGE.
*/		*/


#include <sys/cdefs.h>		#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");		__FBSDID("$FreeBSD$");

		#include "opt_platform.h"

#include <sys/param.h>		#include <sys/param.h>
#include <sys/systm.h>		#include <sys/systm.h>
#include <sys/bus.h>		#include <sys/bus.h>
#include <sys/kernel.h>		#include <sys/kernel.h>
#include <sys/ktr.h>		#include <sys/ktr.h>
#include <sys/module.h>		#include <sys/module.h>
		#include <sys/proc.h>
#include <sys/rman.h>		#include <sys/rman.h>
#include <machine/bus.h>		#include <machine/bus.h>
#include <machine/intr.h>		#include <machine/intr.h>

#include <dev/fdt/fdt_common.h>		#include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h>		#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h>		#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>		#include <dev/ofw/ofw_bus_subr.h>

		#ifdef ARM_INTRNG
		#include "pic_if.h"
		#endif

#define INTC_REVISION 0x00		#define INTC_REVISION 0x00
#define INTC_SYSCONFIG 0x10		#define INTC_SYSCONFIG 0x10
#define INTC_SYSSTATUS 0x14		#define INTC_SYSSTATUS 0x14
#define INTC_SIR_IRQ 0x40		#define INTC_SIR_IRQ 0x40
#define INTC_CONTROL 0x48		#define INTC_CONTROL 0x48
#define INTC_THRESHOLD 0x68		#define INTC_THRESHOLD 0x68
#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))		#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))
#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))		#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))
#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))		#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))
#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))		#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))

		#define INTC_SIR_SPURIOUS_MASK 0xffffff80
		#define INTS_SIR_ACTIVE_MASK 0x7f

		#define INTC_NIRQS 128

		#ifdef ARM_INTRNG
		struct ti_aintc_irqsrc {
		struct intr_irqsrc tai_isrc;
		u_int tai_irq;
		};
		#endif

struct ti_aintc_softc {		struct ti_aintc_softc {
device_t sc_dev;		device_t sc_dev;
struct resource * aintc_res[3];		struct resource * aintc_res[3];
bus_space_tag_t aintc_bst;		bus_space_tag_t aintc_bst;
bus_space_handle_t aintc_bsh;		bus_space_handle_t aintc_bsh;
uint8_t ver;		uint8_t ver;
		#ifdef ARM_INTRNG
		struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS];
		#endif
};		};

static struct resource_spec ti_aintc_spec[] = {		static struct resource_spec ti_aintc_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },		{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }		{ -1, 0 }
};		};

static struct ti_aintc_softc *ti_aintc_sc = NULL;		static struct ti_aintc_softc *ti_aintc_sc = NULL;

#define aintc_read_4(_sc, reg) \		#define aintc_read_4(_sc, reg) \
bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg))		bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg))
#define aintc_write_4(_sc, reg, val) \		#define aintc_write_4(_sc, reg, val) \
bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))		bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))

/* List of compatible strings for FDT tree */		/* List of compatible strings for FDT tree */
static struct ofw_compat_data compat_data[] = {		static struct ofw_compat_data compat_data[] = {
{"ti,am33xx-intc", 1},		{"ti,am33xx-intc", 1},
{"ti,omap2-intc", 1},		{"ti,omap2-intc", 1},
{NULL, 0},		{NULL, 0},
};		};

		#ifdef ARM_INTRNG
		static inline void
		ti_aintc_irq_eoi(struct ti_aintc_softc *sc)
		{

		aintc_write_4(sc, INTC_CONTROL, 1);
		}

		static inline void
		ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq)
		{

		aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F)));
		}

		static inline void
		ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq)
		{

		aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F)));
		}

		static int
		ti_aintc_intr(void *arg)
		{
		uint32_t irq;
		struct ti_aintc_softc *sc = arg;

		/* Get active interrupt */
		irq = aintc_read_4(sc, INTC_SIR_IRQ);
		if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) {
		device_printf(sc->sc_dev,
		"Spurious interrupt detected (0x%08x)\n", irq);
		ti_aintc_irq_eoi(sc);
		return (FILTER_HANDLED);
		}

		/* Only level-sensitive interrupts detection is supported. */
		irq &= INTS_SIR_ACTIVE_MASK;
		if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc,
		curthread->td_intr_frame) != 0) {
		ti_aintc_irq_mask(sc, irq);
		ti_aintc_irq_eoi(sc);
		device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq);
		}

		arm_irq_memory_barrier(irq); /* XXX */
		return (FILTER_HANDLED);
		}

static void		static void
		ti_aintc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
		{
		u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq;
		struct ti_aintc_softc *sc = device_get_softc(dev);

		arm_irq_memory_barrier(irq);
		ti_aintc_irq_unmask(sc, irq);
		}

		static void
		ti_aintc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
		{
		u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq;
		struct ti_aintc_softc *sc = device_get_softc(dev);

		ti_aintc_irq_mask(sc, irq);
		}

		static int
		ti_aintc_map_intr(device_t dev, struct intr_map_data *data,
		struct intr_irqsrc **isrcp)
		{
		struct ti_aintc_softc *sc;

		if (data->type != INTR_MAP_DATA_FDT \|\| data->fdt.ncells != 1 \|\|
		data->fdt.cells[0] >= INTC_NIRQS)
		return (EINVAL);

		sc = device_get_softc(dev);
		*isrcp = &sc->aintc_isrcs[data->fdt.cells[0]].tai_isrc;
		return (0);
		}

		static void
		ti_aintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
		{
		u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq;
		struct ti_aintc_softc *sc = device_get_softc(dev);

		ti_aintc_irq_mask(sc, irq);
		ti_aintc_irq_eoi(sc);
		}

		static void
		ti_aintc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
		{

		ti_aintc_enable_intr(dev, isrc);
		}

		static void
		ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc)
		{

		ti_aintc_irq_eoi(device_get_softc(dev));
		}

		static int
		ti_aintc_pic_attach(struct ti_aintc_softc *sc)
		{
		int error;
		uint32_t irq;
		const char *name;
		intptr_t xref;

		name = device_get_nameunit(sc->sc_dev);
		for (irq = 0; irq < INTC_NIRQS; irq++) {
		sc->aintc_isrcs[irq].tai_irq = irq;

		error = intr_isrc_register(&sc->aintc_isrcs[irq].tai_isrc,
		sc->sc_dev, 0, "%s,%u", name, irq);
		if (error != 0)
		return (error);
		}

		xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev));
		error = intr_pic_register(sc->sc_dev, xref);
		if (error != 0)
		return (error);

		return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc, 0));
		}

		#else
		static void
aintc_post_filter(void *arg)		aintc_post_filter(void *arg)
{		{

arm_irq_memory_barrier(0);		arm_irq_memory_barrier(0);
aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */		aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */
}		}
		#endif

static int		static int
ti_aintc_probe(device_t dev)		ti_aintc_probe(device_t dev)
{		{
if (!ofw_bus_status_okay(dev))		if (!ofw_bus_status_okay(dev))
return (ENXIO);		return (ENXIO);

if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)		if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
Show All 31 Lines	ti_aintc_attach(device_t dev)
aintc_write_4(sc, INTC_SYSCONFIG, 2);		aintc_write_4(sc, INTC_SYSCONFIG, 2);

/* Wait for reset to complete */		/* Wait for reset to complete */
while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));		while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));

/Set Priority Threshold /		/Set Priority Threshold /
aintc_write_4(sc, INTC_THRESHOLD, 0xFF);		aintc_write_4(sc, INTC_THRESHOLD, 0xFF);

		#ifndef ARM_INTRNG
arm_post_filter = aintc_post_filter;		arm_post_filter = aintc_post_filter;
		#else
		if (ti_aintc_pic_attach(sc) != 0) {
		device_printf(dev, "could not attach PIC\n");
		return (ENXIO);
		}
		#endif
return (0);		return (0);
}		}

static device_method_t ti_aintc_methods[] = {		static device_method_t ti_aintc_methods[] = {
DEVMETHOD(device_probe, ti_aintc_probe),		DEVMETHOD(device_probe, ti_aintc_probe),
DEVMETHOD(device_attach, ti_aintc_attach),		DEVMETHOD(device_attach, ti_aintc_attach),

		#ifdef ARM_INTRNG
		DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr),
		DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr),
		DEVMETHOD(pic_map_intr, ti_aintc_map_intr),
		DEVMETHOD(pic_post_filter, ti_aintc_post_filter),
		DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread),
		DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread),
		#endif

{ 0, 0 }		{ 0, 0 }
};		};

static driver_t ti_aintc_driver = {		static driver_t ti_aintc_driver = {
"aintc",		"aintc",
ti_aintc_methods,		ti_aintc_methods,
sizeof(struct ti_aintc_softc),		sizeof(struct ti_aintc_softc),
};		};

static devclass_t ti_aintc_devclass;		static devclass_t ti_aintc_devclass;

EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,		EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,
0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);		0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
SIMPLEBUS_PNP_INFO(compat_data);		SIMPLEBUS_PNP_INFO(compat_data);

		#ifndef ARM_INTRNG
int		int
arm_get_next_irq(int last_irq)		arm_get_next_irq(int last_irq)
{		{
struct ti_aintc_softc *sc = ti_aintc_sc;		struct ti_aintc_softc *sc = ti_aintc_sc;
uint32_t active_irq;		uint32_t active_irq;

/* Get the next active interrupt */		/* Get the next active interrupt */
active_irq = aintc_read_4(sc, INTC_SIR_IRQ);		active_irq = aintc_read_4(sc, INTC_SIR_IRQ);
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void		void
arm_unmask_irq(uintptr_t nb)		arm_unmask_irq(uintptr_t nb)
{		{
struct ti_aintc_softc *sc = ti_aintc_sc;		struct ti_aintc_softc *sc = ti_aintc_sc;

arm_irq_memory_barrier(nb);		arm_irq_memory_barrier(nb);
aintc_write_4(sc, INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));		aintc_write_4(sc, INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F)));
}		}
		#endif