Differential D5726 Diff 14853 head/sys/arm64/arm64/machdep.c

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head/sys/arm64/arm64/machdep.c

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vm_paddr_t physmap[PHYSMAP_SIZE];		vm_paddr_t physmap[PHYSMAP_SIZE];
u_int physmap_idx;		u_int physmap_idx;

struct kva_md_info kmi;		struct kva_md_info kmi;

int64_t dcache_line_size; /* The minimum D cache line size */		int64_t dcache_line_size; /* The minimum D cache line size */
int64_t icache_line_size; /* The minimum I cache line size */		int64_t icache_line_size; /* The minimum I cache line size */
int64_t idcache_line_size; /* The minimum cache line size */		int64_t idcache_line_size; /* The minimum cache line size */
		int64_t dczva_line_size; /* The size of cache line the dc zva zeroes */

static void		static void
cpu_startup(void *dummy)		cpu_startup(void *dummy)
{		{

identify_cpu();		identify_cpu();

vm_ksubmap_init(&kmi);		vm_ksubmap_init(&kmi);
bufinit();		bufinit();
vm_pager_bufferinit();		vm_pager_bufferinit();
}		}

SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);		SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);

int		int
cpu_idle_wakeup(int cpu)		cpu_idle_wakeup(int cpu)
{		{

return (0);		return (0);
}		}

void
bzero(void *buf, size_t len)
{
uint8_t *p;

p = buf;
while(len-- > 0)
*p++ = 0;
}

int		int
fill_regs(struct thread td, struct reg regs)		fill_regs(struct thread td, struct reg regs)
{		{
struct trapframe *frame;		struct trapframe *frame;

frame = td->td_frame;		frame = td->td_frame;
regs->sp = frame->tf_sp;		regs->sp = frame->tf_sp;
regs->lr = frame->tf_lr;		regs->lr = frame->tf_lr;
▲ Show 20 Lines • Show All 645 Lines • ▼ Show 20 Lines	try_load_dtb(caddr_t kmdp)
if (OF_init((void *)dtbp) != 0)		if (OF_init((void *)dtbp) != 0)
panic("OF_init failed with the found device tree");		panic("OF_init failed with the found device tree");
}		}
#endif		#endif

static void		static void
cache_setup(void)		cache_setup(void)
{		{
int dcache_line_shift, icache_line_shift;		int dcache_line_shift, icache_line_shift, dczva_line_shift;
uint32_t ctr_el0;		uint32_t ctr_el0;
		uint32_t dczid_el0;

ctr_el0 = READ_SPECIALREG(ctr_el0);		ctr_el0 = READ_SPECIALREG(ctr_el0);

/* Read the log2 words in each D cache line */		/* Read the log2 words in each D cache line */
dcache_line_shift = CTR_DLINE_SIZE(ctr_el0);		dcache_line_shift = CTR_DLINE_SIZE(ctr_el0);
/* Get the D cache line size */		/* Get the D cache line size */
dcache_line_size = sizeof(int) << dcache_line_shift;		dcache_line_size = sizeof(int) << dcache_line_shift;

/* And the same for the I cache */		/* And the same for the I cache */
icache_line_shift = CTR_ILINE_SIZE(ctr_el0);		icache_line_shift = CTR_ILINE_SIZE(ctr_el0);
icache_line_size = sizeof(int) << icache_line_shift;		icache_line_size = sizeof(int) << icache_line_shift;

idcache_line_size = MIN(dcache_line_size, icache_line_size);		idcache_line_size = MIN(dcache_line_size, icache_line_size);

		dczid_el0 = READ_SPECIALREG(dczid_el0);

		/* Check if dc zva is not prohibited */
		if (dczid_el0 & DCZID_DZP)
		dczva_line_size = 0;
		else {
		/* Same as with above calculations */
		dczva_line_shift = DCZID_BS_SIZE(dczid_el0);
		dczva_line_size = sizeof(int) << dczva_line_shift;
		}
}		}

void		void
initarm(struct arm64_bootparams *abp)		initarm(struct arm64_bootparams *abp)
{		{
struct efi_map_header *efihdr;		struct efi_map_header *efihdr;
struct pcpu *pcpup;		struct pcpu *pcpup;
#ifdef FDT		#ifdef FDT
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