Differential D5726 Diff 14810 sys/arm64/include/armreg.h

Changeset View

Standalone View

sys/arm64/include/armreg.h

	Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
	/* CTR_EL0 - Cache Type Register */			/* CTR_EL0 - Cache Type Register */
	#define CTR_DLINE_SHIFT 16			#define CTR_DLINE_SHIFT 16
	#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)			#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
	#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)			#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
	#define CTR_ILINE_SHIFT 0			#define CTR_ILINE_SHIFT 0
	#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)			#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
	#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)			#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)

				/* DCZID_EL0 - Data Cache Zero ID register */
				#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
				#define DCZID_BS_SHIFT 0
				#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT)
				#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)

	/* ESR_ELx */			/* ESR_ELx */
	#define ESR_ELx_ISS_MASK 0x00ffffff			#define ESR_ELx_ISS_MASK 0x00ffffff
	#define ISS_INSN_FnV (0x01 << 10)			#define ISS_INSN_FnV (0x01 << 10)
	#define ISS_INSN_EA (0x01 << 9)			#define ISS_INSN_EA (0x01 << 9)
	#define ISS_INSN_S1PTW (0x01 << 7)			#define ISS_INSN_S1PTW (0x01 << 7)
	#define ISS_INSN_IFSC_MASK (0x1f << 0)			#define ISS_INSN_IFSC_MASK (0x1f << 0)
	#define ISS_DATA_ISV (0x01 << 24)			#define ISS_DATA_ISV (0x01 << 24)
	#define ISS_DATA_SAS_MASK (0x03 << 22)			#define ISS_DATA_SAS_MASK (0x03 << 22)
	▲ Show 20 Lines • Show All 329 Lines • Show Last 20 Lines