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head/sys/arm64/arm64/gic.c
| Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Lines | |||||
| } | } | ||||
| #endif | #endif | ||||
| int | int | ||||
| arm_gic_attach(device_t dev) | arm_gic_attach(device_t dev) | ||||
| { | { | ||||
| struct arm_gic_softc *sc; | struct arm_gic_softc *sc; | ||||
| int i; | int i; | ||||
| uint32_t icciidr; | uint32_t icciidr, mask; | ||||
| if (arm_gic_sc) | if (arm_gic_sc) | ||||
| return (ENXIO); | return (ENXIO); | ||||
| sc = device_get_softc(dev); | sc = device_get_softc(dev); | ||||
| if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) { | if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) { | ||||
| device_printf(dev, "could not allocate resources\n"); | device_printf(dev, "could not allocate resources\n"); | ||||
| Show All 33 Lines | for (i = 32; i < sc->nirqs; i += 16) { | ||||
| gic_d_write_4(sc, GICD_ICFGR(i >> 4), 0x00000000); | gic_d_write_4(sc, GICD_ICFGR(i >> 4), 0x00000000); | ||||
| } | } | ||||
| /* Disable all interrupts. */ | /* Disable all interrupts. */ | ||||
| for (i = 32; i < sc->nirqs; i += 32) { | for (i = 32; i < sc->nirqs; i += 32) { | ||||
| gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF); | gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF); | ||||
| } | } | ||||
| /* Read the current cpuid mask by reading ITARGETSR{0..7} */ | |||||
| for (i = 0; i < 8; i++) { | |||||
| mask = gic_d_read_4(sc, GICD_ITARGETSR(i)); | |||||
| if (mask != 0) | |||||
| break; | |||||
| } | |||||
| /* No mask found, assume we are on CPU interface 0 */ | |||||
| if (mask == 0) | |||||
| mask = 1; | |||||
| /* Collect the mask in the lower byte */ | |||||
| mask |= mask >> 16; | |||||
| mask |= mask >> 8; | |||||
| /* Distribute this back to the upper bytes */ | |||||
| mask |= mask << 8; | |||||
| mask |= mask << 16; | |||||
| for (i = 0; i < sc->nirqs; i += 4) { | for (i = 0; i < sc->nirqs; i += 4) { | ||||
| gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); | gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); | ||||
| gic_d_write_4(sc, GICD_ITARGETSR(i >> 2), | if (i > 32) { | ||||
| 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24); | gic_d_write_4(sc, GICD_ITARGETSR(i >> 2), mask); | ||||
| } | |||||
| } | } | ||||
| /* Set all the interrupts to be in Group 0 (secure) */ | /* Set all the interrupts to be in Group 0 (secure) */ | ||||
| for (i = 0; i < sc->nirqs; i += 32) { | for (i = 0; i < sc->nirqs; i += 32) { | ||||
| gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); | gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); | ||||
| } | } | ||||
| /* Enable CPU interface */ | /* Enable CPU interface */ | ||||
| ▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines | |||||