Differential D5573 Diff 14627 sys/arm/allwinner/a10/a10_intc.c

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sys/arm/allwinner/a10/a10_intc.c

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				/*-
				* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
				* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.org>
				* All rights reserved.
				*
				* Redistribution and use in source and binary forms, with or without
				* modification, are permitted provided that the following conditions
				* are met:
				* 1. Redistributions of source code must retain the above copyright
				* notice, this list of conditions and the following disclaimer.
				* 2. Redistributions in binary form must reproduce the above copyright
				* notice, this list of conditions and the following disclaimer in the
				* documentation and/or other materials provided with the distribution.
				*
				* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
				* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
				* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
				* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
				* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
				* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
				* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
				* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
				* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
				* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
				* SUCH DAMAGE.
				*/

				#include <sys/cdefs.h>
				__FBSDID("$FreeBSD$");

				#include "opt_platform.h"

				#include <sys/types.h>
				#include <sys/bus.h>
				#include <sys/cpuset.h>
				#include <sys/kernel.h>
				#include <sys/ktr.h>
				#include <sys/module.h>
				#include <sys/mutex.h>
				#include <sys/param.h>
				#include <sys/pcpu.h>
				#include <sys/proc.h>
				#include <sys/rman.h>
				#include <sys/smp.h>
				#include <sys/systm.h>
				#ifdef ARM_INTRNG
				#include <sys/sched.h>
				#endif
				#include <machine/bus.h>
				#include <machine/intr.h>

				#include <dev/fdt/fdt_common.h>
				#include <dev/ofw/openfirm.h>
				#include <dev/ofw/ofw_bus.h>
				#include <dev/ofw/ofw_bus_subr.h>

				#ifdef ARM_INTRNG
				#include "pic_if.h"
				#endif

				/**
				* Interrupt controller registers
				*
				*/
				#define SW_INT_VECTOR_REG 0x00
				#define SW_INT_BASE_ADR_REG 0x04
				#define SW_INT_PROTECTION_REG 0x08
				#define SW_INT_NMI_CTRL_REG 0x0c

				#define SW_INT_IRQ_PENDING_REG0 0x10
				#define SW_INT_IRQ_PENDING_REG1 0x14
				#define SW_INT_IRQ_PENDING_REG2 0x18

				#define SW_INT_FIQ_PENDING_REG0 0x20
				#define SW_INT_FIQ_PENDING_REG1 0x24
				#define SW_INT_FIQ_PENDING_REG2 0x28

				#define SW_INT_SELECT_REG0 0x30
				#define SW_INT_SELECT_REG1 0x34
				#define SW_INT_SELECT_REG2 0x38

				#define SW_INT_ENABLE_REG0 0x40
				#define SW_INT_ENABLE_REG1 0x44
				#define SW_INT_ENABLE_REG2 0x48

				#define SW_INT_MASK_REG0 0x50
				#define SW_INT_MASK_REG1 0x54
				#define SW_INT_MASK_REG2 0x58

				#define SW_INT_IRQNO_ENMI 0

				#define A10_INTC_MAX_NIRQS 80

				#define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
				#define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
				#define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
				#define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
				#define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))

				struct a10_aintc_softc {
				device_t sc_dev;
				struct resource * aintc_res;
				bus_space_tag_t aintc_bst;
				bus_space_handle_t aintc_bsh;
				struct mtx mtx;
				#ifdef ARM_INTRNG
				struct intr_irqsrc ** irqs;
				#endif
				};

				#ifndef ARM_INTRNG
				static struct a10_aintc_softc *a10_aintc_sc = NULL;
				#endif

				#define aintc_read_4(sc, reg) \
				bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg)
				#define aintc_write_4(sc, reg, val) \
				bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val)

				static int a10_intr(void *arg);


				static int
				a10_aintc_probe(device_t dev)
				{

				if (!ofw_bus_status_okay(dev))
				return (ENXIO);

				if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ic"))
				return (ENXIO);
				device_set_desc(dev, "A10 AINTC Interrupt Controller");
				return (BUS_PROBE_DEFAULT);
				}

				static int
				a10_aintc_attach(device_t dev)
				{
				struct a10_aintc_softc *sc = device_get_softc(dev);
				int rid = 0;
				int i;
				#ifdef ARM_INTRNG
				phandle_t xref;
				#endif
				sc->sc_dev = dev;

				#ifndef ARM_INTRNG
				if (a10_aintc_sc)
				goto error;

				a10_aintc_sc = sc;
				#endif

				sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
				&rid, RF_ACTIVE);
				if (!sc->aintc_res) {
				device_printf(dev, "could not allocate resource\n");
				goto error;
				}

				sc->aintc_bst = rman_get_bustag(sc->aintc_res);
				sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);

				mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN);
				#ifdef ARM_INTRNG
				sc->irqs = malloc(A10_INTC_MAX_NIRQS * sizeof (*sc->irqs), M_DEVBUF,
				M_WAITOK \| M_ZERO);
				#endif

				/* Disable & clear all interrupts */
				for (i = 0; i < 3; i++) {
				aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0);
				aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff);
				skraUnsubmitted Done Inline Actions Checking the value for 0 here would avoid the following loop and safe time. skra: Checking the value for 0 here would avoid the following loop and safe time.
				}
				/* enable protection mode*/
				aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01);

				/* config the external interrupt source type*/
				aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00);

				#ifdef ARM_INTRNG
				xref = OF_xref_from_node(ofw_bus_get_node(dev));
				if (intr_pic_register(dev, (intptr_t)xref) != 0) {
				device_printf(dev, "could not register PIC\n");
				goto error;
				}

				if (intr_pic_claim_root(dev, xref, a10_intr, sc,
				A10_INTC_MAX_NIRQS) != 0) {
				device_printf(dev, "could not set PIC as a root\n");
				intr_pic_unregister(dev, xref);
				goto error;
				}

				OF_device_register_xref(xref, dev);
				#endif

				return (0);

				error:
				bus_release_resource(dev, SYS_RES_MEMORY, rid,
				sc->aintc_res);
				return (ENXIO);
				}

				static void
				a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq)
				{
				uint32_t bit, block, value;

				bit = (irq % 32);
				block = (irq / 32);

				mtx_lock_spin(&sc->mtx);
				skraUnsubmitted Done Inline Actions Extra line. skra: Extra line.
				value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
				value \|= (1 << bit);
				aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
				skraUnsubmitted Done Inline Actions -1 is returned when no pending interrupt is found, IMO, the interruption was spurious then. skra: -1 is returned when no pending interrupt is found, IMO, the interruption was spurious then.

				value = aintc_read_4(sc, SW_INT_MASK_REG(block));
				value &= ~(1 << bit);
				aintc_write_4(sc, SW_INT_MASK_REG(block), value);

				if (irq == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */
				skraUnsubmitted Done Inline Actions In not ARM_INTRNG case, the arm_get_next_irq() is called repeatedly until -1 is returned. So, to behave same, a10_pending_irq() should be called here repeatedly. And it's spurious interrupt only when no pending interrupt is found at the beginning. skra: In not ARM_INTRNG case, the arm_get_next_irq() is called repeatedly until -1 is returned. So…
				aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0),
				(1 << SW_INT_IRQNO_ENMI));
				mtx_unlock_spin(&sc->mtx);
				}

				static void
				a10_intr_mask(struct a10_aintc_softc *sc, u_int irq)
				{
				uint32_t bit, block, value;
				skraUnsubmitted Done Inline Actions IMO, a10_pending_irq(sc) returns "int", it's printed as %d, so I would join these ifs, and always print irq. skra: IMO, a10_pending_irq(sc) returns "int", it's printed as %d, so I would join these ifs, and…
				manu_bidouilliste.comAuthorUnsubmitted Done Inline Actions I didn't wanted to print "-1", that's why I've split the printfs' manu_bidouilliste.com: I didn't wanted to print "-1", that's why I've split the printfs'

				bit = (irq % 32);
				block = (irq / 32);
				skraUnsubmitted Done Inline Actions EOI is not in a10_intr_mask() now, so it should be called here. skra: EOI is not in a10_intr_mask() now, so it should be called here.
				manu_bidouilliste.comAuthorUnsubmitted Done Inline Actions True, I'll add that. manu_bidouilliste.com: True, I'll add that.

				mtx_lock_spin(&sc->mtx);
				value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
				value &= ~(1 << bit);
				aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);

				value = aintc_read_4(sc, SW_INT_MASK_REG(block));
				value \|= (1 << bit);
				aintc_write_4(sc, SW_INT_MASK_REG(block), value);
				mtx_unlock_spin(&sc->mtx);
				}

				static int
				a10_pending_irq(struct a10_aintc_softc *sc)
				{
				uint32_t value;
				int i, b;

				for (i = 0; i < 3; i++) {
				value = aintc_read_4(sc, SW_INT_IRQ_PENDING_REG(i));
				for (b = 0; b < 32; b++)
				if (value & (1 << b)) {
				return (i * 32 + b);
				}
				}

				return (-1);
				}

				#ifndef ARM_INTRNG

				int
				arm_get_next_irq(int last_irq)
				{
				return (a10_pending_irq(a10_aintc_sc));
				}

				void
				arm_mask_irq(uintptr_t irq)
				{
				a10_intr_mask(a10_aintc_sc, irq);
				}

				void
				arm_unmask_irq(uintptr_t irq)
				{
				a10_intr_unmask(a10_aintc_sc, irq);
				}

				#else /* ARM_INTRNG */

				static int
				a10_intr(void *arg)
				{
				struct a10_aintc_softc *sc = arg;
				struct intr_irqsrc *isrc;
				u_int irq;

				irq = a10_pending_irq(sc);

				if (irq == -1)
				return (FILTER_HANDLED);

				if (irq > A10_INTC_MAX_NIRQS) {
				device_printf(sc->sc_dev, "Spurious interrupt %d\n", irq);
				return (FILTER_HANDLED);
				}

				isrc = sc->irqs[irq];
				if (isrc == NULL) {
				device_printf(sc->sc_dev, "Stray interrupt %d\n", irq);
				a10_intr_mask(sc, irq);
				return (FILTER_HANDLED);
				}

				intr_irq_dispatch(isrc, curthread->td_intr_frame);
				arm_irq_memory_barrier(irq);
				skraUnsubmitted Done Inline Actions Is it same like a10_intr_disable_intr()? EOI should be here now. skra: Is it same like a10_intr_disable_intr()? EOI should be here now.
				manu_bidouilliste.comAuthorUnsubmitted Done Inline Actions Same as above, I'll add that. manu_bidouilliste.com: Same as above, I'll add that.

				return (FILTER_HANDLED);
				}

				static void
				a10_intr_enable_intr(device_t dev, struct intr_irqsrc *isrc)
				skraUnsubmitted Done Inline Actions Typically, it should be "end of interrupt" here only. I don't see corresponding a10_intr_mask() call in interrupt dispatch path. Should be clearing of pending register enough here? When interrupt is being dispatched, either only pic_post_filter() is called when there is only filter in an interrupt or both pic_pre_ithread() and pic_post_ithread are called when there is (also) a handler. See intr_event_handle() in kern_intr.c. skra: Typically, it should be "end of interrupt" here only. I don't see corresponding a10_intr_mask()…
				{
				struct a10_aintc_softc *sc;
				u_int irq = isrc->isrc_data;

				sc = device_get_softc(dev);
				a10_intr_unmask(sc, irq);
				}

				static void
				a10_intr_enable_source(device_t dev, struct intr_irqsrc *isrc)
				{
				skraUnsubmitted Done Inline Actions Just suggestion. Move the check inside a10_intr_eoi(). You can make the function inlined. But, it's really only up to you. skra: Just suggestion. Move the check inside a10_intr_eoi(). You can make the function inlined. But…
				manu_bidouilliste.comAuthorUnsubmitted Done Inline Actions I wanted to avoid function calls but making it inlined would do the job, I'll change that. manu_bidouilliste.com: I wanted to avoid function calls but making it inlined would do the job, I'll change that.
				struct a10_aintc_softc *sc;
				u_int irq = isrc->isrc_data;

				sc = device_get_softc(dev);
				arm_irq_memory_barrier(irq);
				a10_intr_unmask(sc, irq);
				}

				static void
				a10_intr_disable_source(device_t dev, struct intr_irqsrc *isrc)
				{
				struct a10_aintc_softc *sc;
				u_int irq = isrc->isrc_data;

				sc = device_get_softc(dev);
				a10_intr_mask(sc, irq);
				}

				static int
				a10_intr_register(device_t dev, struct intr_irqsrc isrc, boolean_t is_percpu)
				{
				struct a10_aintc_softc *sc;
				const char *name;
				u_int irq;

				sc = device_get_softc(dev);

				if (isrc->isrc_ncells != 1)
				return (EINVAL);

				irq = isrc->isrc_cells[0];
				if (irq > A10_INTC_MAX_NIRQS)
				return (EINVAL);

				mtx_lock_spin(&sc->mtx);
				if (sc->irqs[irq] != NULL) {
				mtx_unlock_spin(&sc->mtx);
				return (sc->irqs[irq] == isrc ? 0 : EEXIST);
				}
				sc->irqs[irq] = isrc;
				mtx_unlock_spin(&sc->mtx);

				name = device_get_nameunit(dev);
				intr_irq_set_name(isrc, "%s,i%u", name, irq);
				isrc->isrc_nspc_num = irq;
				isrc->isrc_data = irq;
				isrc->isrc_pol = INTR_POLARITY_CONFORM;
				isrc->isrc_trig = INTR_TRIGGER_CONFORM;

				return (0);
				}

				static int
				a10_intr_unregister(device_t dev, struct intr_irqsrc *isrc)
				{
				struct a10_aintc_softc *sc;
				u_int irq = isrc->isrc_data;
				int ret;

				sc = device_get_softc(dev);
				mtx_lock_spin(&sc->mtx);
				if (sc->irqs[irq] != isrc) {
				ret = sc->irqs[irq] == NULL ? 0 : EINVAL;
				mtx_unlock_spin(&sc->mtx);
				return (ret);
				}
				sc->irqs[irq] = NULL;
				isrc->isrc_data = 0;
				mtx_unlock_spin(&sc->mtx);

				intr_irq_set_name(isrc, "");
				return (0);
				}

				static void
				a10_intr_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
				{
				a10_intr_disable_source(dev, isrc);
				}

				static void
				a10_intr_post_ithread(device_t dev, struct intr_irqsrc *isrc)
				{

				arm_irq_memory_barrier(0);
				a10_intr_enable_source(dev, isrc);
				}

				static void
				a10_intr_post_filter(device_t dev, struct intr_irqsrc *isrc)
				{
				struct a10_aintc_softc *sc = device_get_softc(dev);

				arm_irq_memory_barrier(0);
				a10_intr_unmask(sc, isrc->isrc_data);
				}

				#endif /* ARM_INTRNG */

				static device_method_t a10_aintc_methods[] = {
				DEVMETHOD(device_probe, a10_aintc_probe),
				DEVMETHOD(device_attach, a10_aintc_attach),
				#ifdef ARM_INTRNG
				/* Interrupt controller interface */
				DEVMETHOD(pic_disable_source, a10_intr_disable_source),
				DEVMETHOD(pic_enable_intr, a10_intr_enable_intr),
				DEVMETHOD(pic_enable_source, a10_intr_enable_source),
				DEVMETHOD(pic_post_filter, a10_intr_post_filter),
				DEVMETHOD(pic_post_ithread, a10_intr_post_ithread),
				DEVMETHOD(pic_pre_ithread, a10_intr_pre_ithread),
				DEVMETHOD(pic_register, a10_intr_register),
				DEVMETHOD(pic_unregister, a10_intr_unregister),
				#endif
				{ 0, 0 }
				};

				static driver_t a10_aintc_driver = {
				"aintc",
				a10_aintc_methods,
				sizeof(struct a10_aintc_softc),
				};

				static devclass_t a10_aintc_devclass;

				EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0,
				BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST);