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Differential D5633 Diff 14316 sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c

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sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c

Context not available.
* at the default enumeration address (0x18000000). * at the default enumeration address (0x18000000).
*/ */
const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
BHNDB_REGWIN_TABLE_END BHNDB_REGWIN_TABLE_END
Context not available.
* - Compatible with both siba(4) and bcma(4) bus enumeration. * - Compatible with both siba(4) and bcma(4) bus enumeration.
*/ */
const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_CC, .class = BHND_DEVCLASS_CC,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
* - PCI (cid=0x804, revision <= 12) * - PCI (cid=0x804, revision <= 12)
*/ */
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_PCI, .class = BHND_DEVCLASS_PCI,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
* - PCI (cid=0x804, revision >= 13) * - PCI (cid=0x804, revision >= 13)
*/ */
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_PCI, .class = BHND_DEVCLASS_PCI,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_CC, .class = BHND_DEVCLASS_CC,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
* - PCIE (cid=0x820) with ChipCommon (revision <= 31) * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
*/ */
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_PCIE, .class = BHND_DEVCLASS_PCIE,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_CC, .class = BHND_DEVCLASS_CC,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
* - PCIE (cid=0x820) with ChipCommon (revision >= 32) * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
*/ */
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_PCIE, .class = BHND_DEVCLASS_PCIE,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_CC, .class = BHND_DEVCLASS_CC,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
* - PCIE2 (cid=0x83c) * - PCIE2 (cid=0x83c)
*/ */
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = {
.is_hostb_required = true,
.resource_specs = (const struct resource_spec[]) { .resource_specs = (const struct resource_spec[]) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ -1, 0, 0 } { -1, 0, 0 }
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_DYN, .win_type = BHNDB_REGWIN_T_DYN,
.win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE,
.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, .win_spec.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
.res = { SYS_RES_MEMORY, PCIR_BAR(0) } .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
}, },
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_PCIE, .class = BHND_DEVCLASS_PCIE,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.
.win_type = BHNDB_REGWIN_T_CORE, .win_type = BHNDB_REGWIN_T_CORE,
.win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET,
.win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE,
.core = { .win_spec.core = {
.class = BHND_DEVCLASS_CC, .class = BHND_DEVCLASS_CC,
.unit = 0, .unit = 0,
.port = 0, .port = 0,
Context not available.