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sys/arm/allwinner/aintc.c

/*- /*-
* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org> * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.org>
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* 1. Redistributions of source code must retain the above copyright * 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright * 2. Redistributions in binary form must reproduce the above copyright
Show All 11 Lines
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE. * SUCH DAMAGE.
*/ */
#include <sys/cdefs.h> #include <sys/cdefs.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#include "opt_platform.h"
#include <sys/param.h> #include <sys/param.h>
#include <sys/systm.h> #include <sys/systm.h>
#include <sys/bus.h> #include <sys/bus.h>
#include <sys/kernel.h> #include <sys/kernel.h>
#include <sys/ktr.h> #include <sys/ktr.h>
#include <sys/module.h> #include <sys/module.h>
#include <sys/rman.h> #include <sys/rman.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/cpuset.h>
#include <sys/smp.h>
andrewUnsubmitted
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These should be sorted.

andrew: These should be sorted.
#ifdef ARM_INTRNG
#include <sys/sched.h>
#endif
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/intr.h> #include <machine/intr.h>
#include <dev/fdt/fdt_common.h> #include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h> #include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h> #include <dev/ofw/ofw_bus_subr.h>
#ifdef ARM_INTRNG
#include "pic_if.h"
#endif
/** /**
* Interrupt controller registers * Interrupt controller registers
* *
*/ */
#define SW_INT_VECTOR_REG 0x00 #define SW_INT_VECTOR_REG 0x00
#define SW_INT_BASE_ADR_REG 0x04 #define SW_INT_BASE_ADR_REG 0x04
#define SW_INT_PROTECTION_REG 0x08 #define SW_INT_PROTECTION_REG 0x08
#define SW_INT_NMI_CTRL_REG 0x0c #define SW_INT_NMI_CTRL_REG 0x0c
#define SW_INT_IRQ_PENDING_REG0 0x10 #define SW_INT_IRQ_PENDING_REG0 0x10
#define SW_INT_IRQ_PENDING_REG1 0x14 #define SW_INT_IRQ_PENDING_REG1 0x14
#define SW_INT_IRQ_PENDING_REG2 0x18 #define SW_INT_IRQ_PENDING_REG2 0x18
#define SW_INT_FIQ_PENDING_REG0 0x20 #define SW_INT_FIQ_PENDING_REG0 0x20
#define SW_INT_FIQ_PENDING_REG1 0x24 #define SW_INT_FIQ_PENDING_REG1 0x24
#define SW_INT_FIQ_PENDING_REG2 0x28 #define SW_INT_FIQ_PENDING_REG2 0x28
#define SW_INT_SELECT_REG0 0x30 #define SW_INT_SELECT_REG0 0x30
#define SW_INT_SELECT_REG1 0x34 #define SW_INT_SELECT_REG1 0x34
#define SW_INT_SELECT_REG2 0x38 #define SW_INT_SELECT_REG2 0x38
#define SW_INT_ENABLE_REG0 0x40 #define SW_INT_ENABLE_REG0 0x40
#define SW_INT_ENABLE_REG1 0x44 #define SW_INT_ENABLE_REG1 0x44
#define SW_INT_ENABLE_REG2 0x48 #define SW_INT_ENABLE_REG2 0x48
#define SW_INT_MASK_REG0 0x50 #define SW_INT_MASK_REG0 0x50
#define SW_INT_MASK_REG1 0x54 #define SW_INT_MASK_REG1 0x54
#define SW_INT_MASK_REG2 0x58 #define SW_INT_MASK_REG2 0x58
#define SW_INT_IRQNO_ENMI 0 #define SW_INT_IRQNO_ENMI 0
#define A10_INTC_MAX_NIRQS 80
#define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4)) #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
#define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4)) #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
#define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4)) #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
#define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4)) #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
#define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4)) #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
static struct ofw_compat_data compat_data[] = {
{"allwinner,sun4i-a10-ic", 1},
{"allwinner,sun7i-a20-sc-nmi", 1},
andrewUnsubmitted
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Did you mean to remove this?

andrew: Did you mean to remove this?
manu_bidouilliste.comAuthorUnsubmitted
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Yes, this should never had been there, D5663 add correct support for the NMI controller

manu_bidouilliste.com: Yes, this should never had been there, D5663 add correct support for the NMI controller
{NULL, 0}
};
struct a10_aintc_softc { struct a10_aintc_softc {
device_t sc_dev; device_t sc_dev;
struct resource * aintc_res; struct resource * aintc_res;
bus_space_tag_t aintc_bst; bus_space_tag_t aintc_bst;
bus_space_handle_t aintc_bsh; bus_space_handle_t aintc_bsh;
uint8_t ver; struct mtx mtx;
#ifdef ARM_INTRNG
struct intr_irqsrc ** irqs;
#endif
}; };
static struct a10_aintc_softc *a10_aintc_sc = NULL; static struct a10_aintc_softc *a10_aintc_sc = NULL;
andrewUnsubmitted
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Is this used in the intrng case?

andrew: Is this used in the intrng case?
manu_bidouilliste.comAuthorUnsubmitted
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Not anymore, thanks for pointing that out

manu_bidouilliste.com: Not anymore, thanks for pointing that out
#define aintc_read_4(reg) \ #define aintc_read_4(sc, reg) \
bus_space_read_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg) bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg)
#define aintc_write_4(reg, val) \ #define aintc_write_4(sc, reg, val) \
bus_space_write_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg, val) bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val)
static int a10_intr(void *arg);
jmcneillUnsubmitted
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These locking macros don't appear to be used

jmcneill: These locking macros don't appear to be used
static int static int
a10_aintc_probe(device_t dev) a10_aintc_probe(device_t dev)
{ {
if (!ofw_bus_status_okay(dev)) if (!ofw_bus_status_okay(dev))
return (ENXIO); return (ENXIO);
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ic"))
return (ENXIO); return (ENXIO);
device_set_desc(dev, "A10 AINTC Interrupt Controller"); device_set_desc(dev, "A10 AINTC Interrupt Controller");
return (BUS_PROBE_DEFAULT); return (BUS_PROBE_DEFAULT);
} }
static int static int
a10_aintc_attach(device_t dev) a10_aintc_attach(device_t dev)
{ {
struct a10_aintc_softc *sc = device_get_softc(dev); struct a10_aintc_softc *sc = device_get_softc(dev);
int rid = 0; int rid = 0;
int i; int i;
#ifdef ARM_INTRNG
phandle_t xref;
jmcneillUnsubmitted
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OF_xref_from_node returns phandle_t

jmcneill: OF_xref_from_node returns phandle_t
manu_bidouilliste.comAuthorUnsubmitted
Done
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intr_pic_register wants a intptr_t.

manu_bidouilliste.com: intr_pic_register wants a intptr_t.
jmcneillUnsubmitted
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Maybe an explicit cast is in order. Also, "function calls in declarations" thing.

jmcneill: Maybe an explicit cast is in order. Also, "function calls in declarations" thing.
#endif
sc->sc_dev = dev; sc->sc_dev = dev;
if (a10_aintc_sc) if (a10_aintc_sc)
return (ENXIO); goto error;
sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&rid, RF_ACTIVE);
if (!sc->aintc_res) { if (!sc->aintc_res) {
device_printf(dev, "could not allocate resource\n"); device_printf(dev, "could not allocate resource\n");
return (ENXIO); goto error;
} }
sc->aintc_bst = rman_get_bustag(sc->aintc_res); sc->aintc_bst = rman_get_bustag(sc->aintc_res);
sc->aintc_bsh = rman_get_bushandle(sc->aintc_res); sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN);
#ifdef ARM_INTRNG
sc->irqs = malloc(A10_INTC_MAX_NIRQS * sizeof (*sc->irqs), M_DEVBUF,
M_WAITOK | M_ZERO);
#endif
a10_aintc_sc = sc; a10_aintc_sc = sc;
/* Disable & clear all interrupts */ /* Disable & clear all interrupts */
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
aintc_write_4(SW_INT_ENABLE_REG(i), 0); aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0);
aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff); aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff);
} }
/* enable protection mode*/ /* enable protection mode*/
aintc_write_4(SW_INT_PROTECTION_REG, 0x01); aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01);
/* config the external interrupt source type*/ /* config the external interrupt source type*/
aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00); aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00);
#ifdef ARM_INTRNG
xref = OF_xref_from_node(ofw_bus_get_node(dev));
jmcneillUnsubmitted
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space between dev, and xref

jmcneill: space between `dev,` and `xref`
if (intr_pic_register(dev, (intptr_t)xref) != 0) {
device_printf(dev, "could not register PIC\n");
goto error;
}
if (intr_pic_claim_root(dev, xref, a10_intr, sc,
A10_INTC_MAX_NIRQS) != 0) {
device_printf(dev, "could not set PIC as a root\n");
intr_pic_unregister(dev, xref);
goto error;
}
OF_device_register_xref(xref, dev);
#endif
return (0); return (0);
error:
return (ENXIO);
andrewUnsubmitted
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There is no need for this label if we're just returning.

andrew: There is no need for this label if we're just returning.
} }
static device_method_t a10_aintc_methods[] = { static void
DEVMETHOD(device_probe, a10_aintc_probe), a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq)
DEVMETHOD(device_attach, a10_aintc_attach), {
{ 0, 0 } uint32_t bit, block, value;
};
static driver_t a10_aintc_driver = { bit = (irq % 32);
"aintc", block = (irq / 32);
a10_aintc_methods,
sizeof(struct a10_aintc_softc),
};
static devclass_t a10_aintc_devclass; mtx_lock_spin(&sc->mtx);
value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
value |= (1 << bit);
aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0, value = aintc_read_4(sc, SW_INT_MASK_REG(block));
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST); value &= ~(1 << bit);
aintc_write_4(sc, SW_INT_MASK_REG(block), value);
int if (irq == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */
arm_get_next_irq(int last_irq) aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0),
(1 << SW_INT_IRQNO_ENMI));
mtx_unlock_spin(&sc->mtx);
}
static void
a10_intr_mask(struct a10_aintc_softc *sc, u_int irq)
{ {
uint32_t bit, block, value;
bit = (irq % 32);
block = (irq / 32);
mtx_lock_spin(&sc->mtx);
value = aintc_read_4(sc, SW_INT_ENABLE_REG(block));
value &= ~(1 << bit);
aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);
value = aintc_read_4(sc, SW_INT_MASK_REG(block));
value |= (1 << bit);
aintc_write_4(sc, SW_INT_MASK_REG(block), value);
mtx_unlock_spin(&sc->mtx);
}
static int
a10_pending_irq(struct a10_aintc_softc *sc)
jmcneillUnsubmitted
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space between if and (irq

jmcneill: space between `if` and `(irq`
{
uint32_t value; uint32_t value;
int i, b; int i, b;
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
value = aintc_read_4(SW_INT_IRQ_PENDING_REG(i)); value = aintc_read_4(sc, SW_INT_IRQ_PENDING_REG(i));
for (b = 0; b < 32; b++) for (b = 0; b < 32; b++)
if (value & (1 << b)) { if (value & (1 << b)) {
return (i * 32 + b); return (i * 32 + b);
} }
} }
return (-1); return (-1);
} }
#ifndef ARM_INTRNG
int
arm_get_next_irq(int last_irq)
{
return (a10_pending_irq(a10_aintc_sc));
}
void void
arm_mask_irq(uintptr_t nb) arm_mask_irq(uintptr_t irq)
{ {
uint32_t bit, block, value; a10_intr_mask(a10_aintc_sc, irq);
}
bit = (nb % 32); void
block = (nb / 32); arm_unmask_irq(uintptr_t irq)
{
a10_intr_unmask(a10_aintc_sc, irq);
}
value = aintc_read_4(SW_INT_ENABLE_REG(block)); #else /* ARM_INTRNG */
value &= ~(1 << bit);
aintc_write_4(SW_INT_ENABLE_REG(block), value);
value = aintc_read_4(SW_INT_MASK_REG(block)); static int
value |= (1 << bit); a10_intr(void *arg)
aintc_write_4(SW_INT_MASK_REG(block), value); {
struct a10_aintc_softc *sc = arg;
struct intr_irqsrc *isrc;
u_int irq;
mtx_lock_spin(&sc->mtx);
andrewUnsubmitted
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What is this protecting?

andrew: What is this protecting?
manu_bidouilliste.comAuthorUnsubmitted
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Might be a leftover of some old code, I'll check that.

manu_bidouilliste.com: Might be a leftover of some old code, I'll check that.
irq = a10_pending_irq(sc);
mtx_unlock_spin(&sc->mtx);
if (irq == -1)
return (FILTER_HANDLED);
if (irq > A10_INTC_MAX_NIRQS) {
device_printf(sc->sc_dev, "Spurious interrupt %d\n", irq);
return (FILTER_HANDLED);
} }
void isrc = sc->irqs[irq];
arm_unmask_irq(uintptr_t nb) if (isrc == NULL) {
device_printf(sc->sc_dev, "Stray interrupt %d\n", irq);
a10_intr_mask(sc, irq);
return (FILTER_HANDLED);
}
intr_irq_dispatch(isrc, curthread->td_intr_frame);
arm_irq_memory_barrier(irq);
return (FILTER_HANDLED);
}
static void
a10_intr_enable_intr(device_t dev, struct intr_irqsrc *isrc)
{ {
uint32_t bit, block, value; struct a10_aintc_softc *sc;
u_int irq = isrc->isrc_data;
jmcneillUnsubmitted
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Avoid function calls in declarations

jmcneill: Avoid function calls in declarations
bit = (nb % 32); sc = device_get_softc(dev);
block = (nb / 32); a10_intr_unmask(sc, irq);
}
value = aintc_read_4(SW_INT_ENABLE_REG(block)); static void
value |= (1 << bit); a10_intr_enable_source(device_t dev, struct intr_irqsrc *isrc)
aintc_write_4(SW_INT_ENABLE_REG(block), value); {
struct a10_aintc_softc *sc;
jmcneillUnsubmitted
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Avoid function calls in declarations

jmcneill: Avoid function calls in declarations
u_int irq = isrc->isrc_data;
value = aintc_read_4(SW_INT_MASK_REG(block)); sc = device_get_softc(dev);
value &= ~(1 << bit); arm_irq_memory_barrier(irq);
aintc_write_4(SW_INT_MASK_REG(block), value); a10_intr_unmask(sc, irq);
}
if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */ static void
aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI)); a10_intr_disable_source(device_t dev, struct intr_irqsrc *isrc)
{
jmcneillUnsubmitted
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Avoid function calls in declarations

jmcneill: Avoid function calls in declarations
struct a10_aintc_softc *sc;
u_int irq = isrc->isrc_data;
sc = device_get_softc(dev);
a10_intr_mask(sc, irq);
} }
static int
a10_intr_register(device_t dev, struct intr_irqsrc *isrc, boolean_t *is_percpu)
jmcneillUnsubmitted
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Avoid function calls in declarations

jmcneill: Avoid function calls in declarations
{
struct a10_aintc_softc *sc;
const char *name;
u_int irq;
sc = device_get_softc(dev);
if (isrc->isrc_ncells != 1)
return (EINVAL);
irq = isrc->isrc_cells[0];
if (irq > A10_INTC_MAX_NIRQS)
return (EINVAL);
jmcneillUnsubmitted
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You should evaluate this condition before unlocking the mutex.

jmcneill: You should evaluate this condition before unlocking the mutex.
mtx_lock_spin(&sc->mtx);
if (sc->irqs[irq] != NULL) {
mtx_unlock_spin(&sc->mtx);
return (sc->irqs[irq] == isrc ? 0 : EEXIST);
}
sc->irqs[irq] = isrc;
mtx_unlock_spin(&sc->mtx);
name = device_get_nameunit(dev);
intr_irq_set_name(isrc, "%s,i%u", name, irq);
isrc->isrc_nspc_num = irq;
isrc->isrc_data = irq;
isrc->isrc_pol = INTR_POLARITY_CONFORM;
isrc->isrc_trig = INTR_TRIGGER_CONFORM;
return (0);
}
static int
a10_intr_unregister(device_t dev, struct intr_irqsrc *isrc)
{
struct a10_aintc_softc *sc;
u_int irq = isrc->isrc_data;
int ret;
jmcneillUnsubmitted
Done
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You should evaluate this condition before unlocking the mutex.

jmcneill: You should evaluate this condition before unlocking the mutex.
sc = device_get_softc(dev);
mtx_lock_spin(&sc->mtx);
if (sc->irqs[irq] != isrc) {
ret = sc->irqs[irq] == NULL ? 0 : EINVAL;
mtx_unlock_spin(&sc->mtx);
return (ret);
}
sc->irqs[irq] = NULL;
isrc->isrc_data = 0;
mtx_unlock_spin(&sc->mtx);
intr_irq_set_name(isrc, "");
return (0);
}
static void
a10_intr_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
{
a10_intr_disable_source(dev, isrc);
}
static void
a10_intr_post_ithread(device_t dev, struct intr_irqsrc *isrc)
{
arm_irq_memory_barrier(0);
a10_intr_enable_source(dev, isrc);
}
static void
a10_intr_post_filter(device_t dev, struct intr_irqsrc *isrc)
{
struct a10_aintc_softc *sc = device_get_softc(dev);
arm_irq_memory_barrier(0);
a10_intr_unmask(sc, isrc->isrc_data);
}
#endif /* ARM_INTRNG */
static device_method_t a10_aintc_methods[] = {
DEVMETHOD(device_probe, a10_aintc_probe),
DEVMETHOD(device_attach, a10_aintc_attach),
#ifdef ARM_INTRNG
/* Interrupt controller interface */
DEVMETHOD(pic_disable_source, a10_intr_disable_source),
DEVMETHOD(pic_enable_intr, a10_intr_enable_intr),
DEVMETHOD(pic_enable_source, a10_intr_enable_source),
DEVMETHOD(pic_post_filter, a10_intr_post_filter),
DEVMETHOD(pic_post_ithread, a10_intr_post_ithread),
DEVMETHOD(pic_pre_ithread, a10_intr_pre_ithread),
DEVMETHOD(pic_register, a10_intr_register),
DEVMETHOD(pic_unregister, a10_intr_unregister),
#endif
{ 0, 0 }
};
static driver_t a10_aintc_driver = {
"aintc",
a10_aintc_methods,
sizeof(struct a10_aintc_softc),
};
static devclass_t a10_aintc_devclass;
EARLY_DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_FIRST);