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Show First 20 Lines • Show All 471 Lines • ▼ Show 20 Lines	xen_hvm_cpu_init(void)
info.offset = vtophys(vcpu_info) - trunc_page(vtophys(vcpu_info));		info.offset = vtophys(vcpu_info) - trunc_page(vtophys(vcpu_info));

rc = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, cpu, &info);		rc = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, cpu, &info);
if (rc != 0)		if (rc != 0)
DPCPU_SET(vcpu_info, &HYPERVISOR_shared_info->vcpu_info[cpu]);		DPCPU_SET(vcpu_info, &HYPERVISOR_shared_info->vcpu_info[cpu]);
else		else
DPCPU_SET(vcpu_info, vcpu_info);		DPCPU_SET(vcpu_info, vcpu_info);
}		}
SYSINIT(xen_hvm_cpu_init, SI_SUB_INTR, SI_ORDER_FIRST, xen_hvm_cpu_init, NULL);		SYSINIT(xen_hvm_cpu_init, SI_SUB_INTR, SI_ORDER_FIRST, xen_hvm_cpu_init);

bool		bool
xen_has_iommu_maps(void)		xen_has_iommu_maps(void)
{		{
uint32_t regs[4];		uint32_t regs[4];

KASSERT(xen_cpuid_base != 0, ("Invalid base Xen CPUID leaf"));		KASSERT(xen_cpuid_base != 0, ("Invalid base Xen CPUID leaf"));
cpuid_count(xen_cpuid_base + 4, 0, regs);		cpuid_count(xen_cpuid_base + 4, 0, regs);

return (regs[0] & XEN_HVM_CPUID_IOMMU_MAPPINGS);		return (regs[0] & XEN_HVM_CPUID_IOMMU_MAPPINGS);
}		}