Differential D40263 Diff 122648 sys/arm64/arm64/gic_v3_var.h

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sys/arm64/arm64/gic_v3_var.h

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	#define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0"			#define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0"

	DECLARE_CLASS(gic_v3_driver);			DECLARE_CLASS(gic_v3_driver);

	struct gic_v3_irqsrc;			struct gic_v3_irqsrc;

	struct redist_pcpu {			struct redist_pcpu {
	struct resource res; /* mem resource for redist */			struct resource res; / mem resource for redist */
	vm_offset_t pend_base;			vm_offset_t pend_base;
				bus_size_t offset;
	bool lpi_enabled; /* redist LPI configured? */			bool lpi_enabled; /* redist LPI configured? */
	};			};

	struct gic_redists {			struct gic_redists {
	/*			/*
	* Re-Distributor region description.			* Re-Distributor region description.
	* We will have few of those depending			* We will have few of those depending
	* on the #redistributor-regions property in FDT.			* on the #redistributor-regions property in FDT.
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	})			})

	/* GIC Re-Distributor accessors (per-CPU) */			/* GIC Re-Distributor accessors (per-CPU) */
	#define gic_r_read(sc, len, reg) \			#define gic_r_read(sc, len, reg) \
	({ \			({ \
	u_int cpu = PCPU_GET(cpuid); \			u_int cpu = PCPU_GET(cpuid); \
	\			\
	bus_read_##len( \			bus_read_##len( \
	&(sc)->gic_redists.pcpu[cpu]->res, \			(sc)->gic_redists.pcpu[cpu]->res, \
	(reg)); \			(sc)->gic_redists.pcpu[cpu]->offset + (reg)); \
	})			})

	#define gic_r_write(sc, len, reg, val) \			#define gic_r_write(sc, len, reg, val) \
	({ \			({ \
	u_int cpu = PCPU_GET(cpuid); \			u_int cpu = PCPU_GET(cpuid); \
	\			\
	bus_write_##len( \			bus_write_##len( \
	&(sc)->gic_redists.pcpu[cpu]->res, \			(sc)->gic_redists.pcpu[cpu]->res, \
	(reg), (val)); \			(sc)->gic_redists.pcpu[cpu]->offset + (reg), \
				(val)); \
	})			})

	#endif /* _GIC_V3_VAR_H_ */			#endif /* _GIC_V3_VAR_H_ */