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sys/dev/ice/ice_common.h
/* SPDX-License-Identifier: BSD-3-Clause */ | /* SPDX-License-Identifier: BSD-3-Clause */ | ||||
/* Copyright (c) 2022, Intel Corporation | /* Copyright (c) 2023, Intel Corporation | ||||
* All rights reserved. | * All rights reserved. | ||||
* | * | ||||
* Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
* modification, are permitted provided that the following conditions are met: | * modification, are permitted provided that the following conditions are met: | ||||
* | * | ||||
* 1. Redistributions of source code must retain the above copyright notice, | * 1. Redistributions of source code must retain the above copyright notice, | ||||
* this list of conditions and the following disclaimer. | * this list of conditions and the following disclaimer. | ||||
* | * | ||||
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void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); | void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); | ||||
bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); | bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); | ||||
void ice_set_umac_shared(struct ice_hw *hw); | void ice_set_umac_shared(struct ice_hw *hw); | ||||
enum ice_status ice_init_hw(struct ice_hw *hw); | enum ice_status ice_init_hw(struct ice_hw *hw); | ||||
void ice_deinit_hw(struct ice_hw *hw); | void ice_deinit_hw(struct ice_hw *hw); | ||||
enum ice_status ice_check_reset(struct ice_hw *hw); | enum ice_status ice_check_reset(struct ice_hw *hw); | ||||
enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); | enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); | ||||
enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); | enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); | ||||
enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); | enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); | ||||
void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); | void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); | ||||
void ice_destroy_all_ctrlq(struct ice_hw *hw); | void ice_destroy_all_ctrlq(struct ice_hw *hw); | ||||
enum ice_status | enum ice_status | ||||
ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, | ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, | ||||
struct ice_rq_event_info *e, u16 *pending); | struct ice_rq_event_info *e, u16 *pending); | ||||
enum ice_status | enum ice_status | ||||
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ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, | ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, | ||||
struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, | struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, | ||||
enum ice_adminq_opc opc, struct ice_sq_cd *cd); | enum ice_adminq_opc opc, struct ice_sq_cd *cd); | ||||
enum ice_status | enum ice_status | ||||
ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, | ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, | ||||
struct ice_aq_desc *desc, void *buf, u16 buf_size, | struct ice_aq_desc *desc, void *buf, u16 buf_size, | ||||
struct ice_sq_cd *cd); | struct ice_sq_cd *cd); | ||||
void ice_clear_pxe_mode(struct ice_hw *hw); | void ice_clear_pxe_mode(struct ice_hw *hw); | ||||
enum ice_status ice_get_caps(struct ice_hw *hw); | enum ice_status ice_get_caps(struct ice_hw *hw); | ||||
void ice_set_safe_mode_caps(struct ice_hw *hw); | void ice_set_safe_mode_caps(struct ice_hw *hw); | ||||
enum ice_status | enum ice_status | ||||
ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, | ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, | ||||
u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, | u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, | ||||
u16 *ret_next_table, u32 *ret_next_index, | u16 *ret_next_table, u32 *ret_next_index, | ||||
struct ice_sq_cd *cd); | struct ice_sq_cd *cd); | ||||
enum ice_status ice_set_mac_type(struct ice_hw *hw); | enum ice_status ice_set_mac_type(struct ice_hw *hw); | ||||
/* Define a macro that will align a pointer to point to the next memory address | /* Define a macro that will align a pointer to point to the next memory address | ||||
* that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For | * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For | ||||
* example, given the variable pointer = 0x1006, then after the following call: | * example, given the variable pointer = 0x1006, then after the following call: | ||||
* | * | ||||
* pointer = ICE_ALIGN(pointer, 4) | * pointer = ICE_ALIGN(pointer, 4) | ||||
* | * | ||||
* ... the value of pointer would equal 0x1008, since 0x1008 is the next | * ... the value of pointer would equal 0x1008, since 0x1008 is the next | ||||
* address after 0x1006 which is divisible by 4. | * address after 0x1006 which is divisible by 4. | ||||
*/ | */ | ||||
#define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) | #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) | ||||
#define ice_arr_elem_idx(idx, val) [(idx)] = (val) | |||||
enum ice_status | enum ice_status | ||||
ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, | ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, | ||||
u32 rxq_index); | u32 rxq_index); | ||||
enum ice_status | |||||
ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, | |||||
u32 rxq_index); | |||||
enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); | enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); | ||||
enum ice_status | enum ice_status | ||||
ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); | ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); | ||||
enum ice_status | enum ice_status | ||||
ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, | ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, | ||||
struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, | struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, | ||||
u32 tx_cmpltnq_index); | u32 tx_cmpltnq_index); | ||||
enum ice_status | enum ice_status | ||||
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bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); | bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); | ||||
enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); | enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); | ||||
void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); | void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); | ||||
extern const struct ice_ctx_ele ice_tlan_ctx_info[]; | extern const struct ice_ctx_ele ice_tlan_ctx_info[]; | ||||
enum ice_status | enum ice_status | ||||
ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, | ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, | ||||
const struct ice_ctx_ele *ce_info); | const struct ice_ctx_ele *ce_info); | ||||
enum ice_status | |||||
ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); | |||||
enum ice_status | enum ice_status | ||||
ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, | ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, | ||||
void *buf, u16 buf_size, struct ice_sq_cd *cd); | void *buf, u16 buf_size, struct ice_sq_cd *cd); | ||||
enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); | enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); | ||||
enum ice_status | enum ice_status | ||||
ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, | ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, | ||||
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enum ice_status | enum ice_status | ||||
ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, | ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, | ||||
struct ice_sq_cd *cd); | struct ice_sq_cd *cd); | ||||
enum ice_status | enum ice_status | ||||
ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, | ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, | ||||
u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, | u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, | ||||
bool write, struct ice_sq_cd *cd); | bool write, struct ice_sq_cd *cd); | ||||
u32 ice_get_link_speed(u16 index); | |||||
enum ice_status | enum ice_status | ||||
ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, | ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, | ||||
struct ice_aqc_link_topo_params *topo_params, | struct ice_aqc_link_topo_params *topo_params, | ||||
struct ice_sq_cd *cd); | struct ice_sq_cd *cd); | ||||
enum ice_status | enum ice_status | ||||
ice_aq_read_topo_dev_nvm(struct ice_hw *hw, | ice_aq_read_topo_dev_nvm(struct ice_hw *hw, | ||||
struct ice_aqc_link_topo_params *topo_params, | struct ice_aqc_link_topo_params *topo_params, | ||||
u32 start_address, u8 *buf, u8 buf_size, | u32 start_address, u8 *buf, u8 buf_size, | ||||
struct ice_sq_cd *cd); | struct ice_sq_cd *cd); | ||||
enum ice_status | enum ice_status | ||||
ice_aq_get_port_options(struct ice_hw *hw, | ice_aq_get_port_options(struct ice_hw *hw, | ||||
struct ice_aqc_get_port_options_elem *options, | struct ice_aqc_get_port_options_elem *options, | ||||
u8 *option_count, u8 lport, bool lport_valid, | u8 *option_count, u8 lport, bool lport_valid, | ||||
u8 *active_option_idx, bool *active_option_valid); | u8 *active_option_idx, bool *active_option_valid, | ||||
u8 *pending_option_idx, bool *pending_option_valid); | |||||
enum ice_status | enum ice_status | ||||
ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); | ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, | ||||
u8 new_option); | |||||
enum ice_status | enum ice_status | ||||
__ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); | __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); | ||||
enum ice_status | enum ice_status | ||||
__ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); | __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); | ||||
enum ice_status | enum ice_status | ||||
ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, | ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, | ||||
u16 *max_rdmaqs); | u16 *max_rdmaqs); | ||||
enum ice_status | enum ice_status | ||||
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