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Differential D5471 Diff 13837 head/sys/powerpc/booke/pmap.c

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head/sys/powerpc/booke/pmap.c

Show First 20 Lines • Show All 334 Lines • ▼ Show 20 Linesstatic void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
vm_size_t); vm_size_t);
static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t,
void **); void **);
static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t,
void *); void *);
static void mmu_booke_scan_init(mmu_t); static void mmu_booke_scan_init(mmu_t);
static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m);
static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr);
static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr,
vm_size_t sz, vm_memattr_t mode);
static mmu_method_t mmu_booke_methods[] = { static mmu_method_t mmu_booke_methods[] = {
/* pmap dispatcher interface */ /* pmap dispatcher interface */
MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
MMUMETHOD(mmu_copy, mmu_booke_copy), MMUMETHOD(mmu_copy, mmu_booke_copy),
MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
MMUMETHOD(mmu_enter, mmu_booke_enter), MMUMETHOD(mmu_enter, mmu_booke_enter),
Show All 36 Linesstatic mmu_method_t mmu_booke_methods[] = {
MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
MMUMETHOD(mmu_kenter, mmu_booke_kenter), MMUMETHOD(mmu_kenter, mmu_booke_kenter),
MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
MMUMETHOD(mmu_kextract, mmu_booke_kextract), MMUMETHOD(mmu_kextract, mmu_booke_kextract),
/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
MMUMETHOD(mmu_change_attr, mmu_booke_change_attr),
/* dumpsys() support */ /* dumpsys() support */
MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), MMUMETHOD(mmu_scan_init, mmu_booke_scan_init),
{ 0, 0 } { 0, 0 }
}; };
Show All 11 Lines if (ma != VM_MEMATTR_DEFAULT) {
case VM_MEMATTR_UNCACHEABLE: case VM_MEMATTR_UNCACHEABLE:
return (MAS2_I | MAS2_G); return (MAS2_I | MAS2_G);
case VM_MEMATTR_WRITE_COMBINING: case VM_MEMATTR_WRITE_COMBINING:
case VM_MEMATTR_WRITE_BACK: case VM_MEMATTR_WRITE_BACK:
case VM_MEMATTR_PREFETCHABLE: case VM_MEMATTR_PREFETCHABLE:
return (MAS2_I); return (MAS2_I);
case VM_MEMATTR_WRITE_THROUGH: case VM_MEMATTR_WRITE_THROUGH:
return (MAS2_W | MAS2_M); return (MAS2_W | MAS2_M);
case VM_MEMATTR_CACHEABLE:
return (MAS2_M);
} }
} }
/* /*
* Assume the page is cache inhibited and access is guarded unless * Assume the page is cache inhibited and access is guarded unless
* it's in our available memory array. * it's in our available memory array.
*/ */
attrib = _TLB_ENTRY_IO; attrib = _TLB_ENTRY_IO;
▲ Show 20 Lines • Show All 2,463 Lines • ▼ Show 20 Lines
*/ */
static int static int
mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
vm_paddr_t *locked_pa) vm_paddr_t *locked_pa)
{ {
/* XXX: this should be implemented at some point */ /* XXX: this should be implemented at some point */
return (0); return (0);
}
static int
mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz,
vm_memattr_t mode)
{
vm_offset_t va;
pte_t *pte;
int i, j;
/* Check TLB1 mappings */
for (i = 0; i < tlb1_idx; i++) {
if (!(tlb1[i].mas1 & MAS1_VALID))
continue;
if (addr >= tlb1[i].virt && addr < tlb1[i].virt + tlb1[i].size)
break;
}
if (i < tlb1_idx) {
/* Only allow full mappings to be modified for now. */
/* Validate the range. */
for (j = i, va = addr; va < addr + sz; va += tlb1[j].size, j++) {
if (va != tlb1[j].virt || (sz - (va - addr) < tlb1[j].size))
return (EINVAL);
}
for (va = addr; va < addr + sz; va += tlb1[i].size, i++) {
tlb1[i].mas2 &= ~MAS2_WIMGE_MASK;
tlb1[i].mas2 |= tlb_calc_wimg(tlb1[i].phys, mode);
/*
* Write it out to the TLB. Should really re-sync with other
* cores.
*/
tlb1_write_entry(i);
}
return (0);
}
/* Not in TLB1, try through pmap */
/* First validate the range. */
for (va = addr; va < addr + sz; va += PAGE_SIZE) {
pte = pte_find(mmu, kernel_pmap, va);
if (pte == NULL || !PTE_ISVALID(pte))
return (EINVAL);
}
mtx_lock_spin(&tlbivax_mutex);
tlb_miss_lock();
for (va = addr; va < addr + sz; va += PAGE_SIZE) {
pte = pte_find(mmu, kernel_pmap, va);
*pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
*pte |= tlb_calc_wimg(PTE_PA(pte), mode << PTE_MAS2_SHIFT);
tlb0_flush_entry(va);
}
tlb_miss_unlock();
mtx_unlock_spin(&tlbivax_mutex);
return (pte_vatopa(mmu, kernel_pmap, va));
} }
/**************************************************************************/ /**************************************************************************/
/* TID handling */ /* TID handling */
/**************************************************************************/ /**************************************************************************/
/* /*
* Allocate a TID. If necessary, steal one from someone else. * Allocate a TID. If necessary, steal one from someone else.
▲ Show 20 Lines • Show All 587 Lines • Show Last 20 Lines