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sys/arm/ti/ti_sysc.c
Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Lines | parse_regfields(struct ti_sysc_softc *sc) { | ||||
if (!(parent_size_cells == 1 || parent_size_cells == 2)) { | if (!(parent_size_cells == 1 || parent_size_cells == 2)) { | ||||
DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n"); | DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n"); | ||||
return (ENXIO); | return (ENXIO); | ||||
} | } | ||||
/* Grab the content of reg properties */ | /* Grab the content of reg properties */ | ||||
nreg = OF_getproplen(node, "reg"); | nreg = OF_getproplen(node, "reg"); | ||||
if (nreg <= 0) | |||||
return (ENXIO); | |||||
reg = malloc(nreg, M_DEVBUF, M_WAITOK); | reg = malloc(nreg, M_DEVBUF, M_WAITOK); | ||||
OF_getencprop(node, "reg", reg, nreg); | OF_getencprop(node, "reg", reg, nreg); | ||||
/* Make sure address & size are 0 */ | /* Make sure address & size are 0 */ | ||||
for (idx = 0; idx < REG_MAX; idx++) { | for (idx = 0; idx < REG_MAX; idx++) { | ||||
sc->reg[idx].address = 0; | sc->reg[idx].address = 0; | ||||
sc->reg[idx].size = 0; | sc->reg[idx].size = 0; | ||||
} | } | ||||
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