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head/sys/dev/ixl/if_ixl.c
| Show First 20 Lines • Show All 2,240 Lines • ▼ Show 20 Lines | ixl_configure_msix(struct ixl_pf *pf) | ||||
| wr32(hw, I40E_PFINT_DYN_CTL0, | wr32(hw, I40E_PFINT_DYN_CTL0, | ||||
| I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | | I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | | ||||
| I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | ||||
| wr32(hw, I40E_PFINT_STAT_CTL0, 0); | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | ||||
| /* Next configure the queues */ | /* Next configure the queues */ | ||||
| for (int i = 0; i < vsi->num_queues; i++, vector++) { | for (int i = 0; i < vsi->num_queues; i++, vector++) { | ||||
| wr32(hw, I40E_PFINT_DYN_CTLN(i), i); | wr32(hw, I40E_PFINT_DYN_CTLN(i), 0); | ||||
| /* First queue type is RX / type 0 */ | |||||
| wr32(hw, I40E_PFINT_LNKLSTN(i), i); | wr32(hw, I40E_PFINT_LNKLSTN(i), i); | ||||
| reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | | reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | | ||||
| (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | ||||
| (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | ||||
| (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | | (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | | ||||
| (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | ||||
| wr32(hw, I40E_QINT_RQCTL(i), reg); | wr32(hw, I40E_QINT_RQCTL(i), reg); | ||||
| reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | ||||
| (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | ||||
| (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | ||||
| ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | ||||
| (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | ||||
| if (i == (vsi->num_queues - 1)) | |||||
| reg |= (IXL_QUEUE_EOL | |||||
| << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |||||
| wr32(hw, I40E_QINT_TQCTL(i), reg); | wr32(hw, I40E_QINT_TQCTL(i), reg); | ||||
| } | } | ||||
| } | } | ||||
| /* | /* | ||||
| * Configure for MSI single vector operation | * Configure for MSI single vector operation | ||||
| */ | */ | ||||
| static void | static void | ||||
| ▲ Show 20 Lines • Show All 4,417 Lines • Show Last 20 Lines | |||||