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stable/10/sys/dev/ixgbe/ixgbe_x550.c
Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
* Returns status code | * Returns status code | ||||
**/ | **/ | ||||
static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) | static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) | ||||
{ | { | ||||
return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); | return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_get_cs4227_status - Return CS4227 status | |||||
* @hw: pointer to hardware structure | |||||
* | |||||
* Returns error if CS4227 not successfully initialized | |||||
**/ | |||||
static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) | |||||
{ | |||||
s32 status; | |||||
u16 value = 0; | |||||
u16 reg_slice, reg_val; | |||||
u8 retry; | |||||
for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) { | |||||
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB, | |||||
&value); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
if (value == IXGBE_CS4227_GLOBAL_ID_VALUE) | |||||
break; | |||||
msec_delay(IXGBE_CS4227_CHECK_DELAY); | |||||
} | |||||
if (value != IXGBE_CS4227_GLOBAL_ID_VALUE) | |||||
return IXGBE_ERR_PHY; | |||||
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
/* If this is the first time after power-on, check the ucode. | |||||
* Otherwise, this will disrupt link on all ports. Because we | |||||
* can only do this the first time, we must check all ports, | |||||
* not just our own. | |||||
*/ | |||||
if (value != IXGBE_CS4227_SCRATCH_VALUE) { | |||||
reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | |||||
status = ixgbe_write_cs4227(hw, reg_slice, | |||||
reg_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | |||||
status = ixgbe_write_cs4227(hw, reg_slice, | |||||
reg_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | |||||
status = ixgbe_write_cs4227(hw, reg_slice, | |||||
reg_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | |||||
status = ixgbe_write_cs4227(hw, reg_slice, | |||||
reg_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
msec_delay(10); | |||||
} | |||||
/* Verify that the ucode is operational on all ports. */ | |||||
reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; | |||||
reg_val = 0xFFFF; | |||||
status = ixgbe_read_cs4227(hw, reg_slice, ®_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
if (reg_val != 0) | |||||
return IXGBE_ERR_PHY; | |||||
reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; | |||||
reg_val = 0xFFFF; | |||||
status = ixgbe_read_cs4227(hw, reg_slice, ®_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
if (reg_val != 0) | |||||
return IXGBE_ERR_PHY; | |||||
reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); | |||||
reg_val = 0xFFFF; | |||||
status = ixgbe_read_cs4227(hw, reg_slice, ®_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
if (reg_val != 0) | |||||
return IXGBE_ERR_PHY; | |||||
reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); | |||||
reg_val = 0xFFFF; | |||||
status = ixgbe_read_cs4227(hw, reg_slice, ®_val); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
if (reg_val != 0) | |||||
return IXGBE_ERR_PHY; | |||||
/* Set scratch for next time. */ | |||||
status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, | |||||
IXGBE_CS4227_SCRATCH_VALUE); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); | |||||
if (status != IXGBE_SUCCESS) | |||||
return status; | |||||
if (value != IXGBE_CS4227_SCRATCH_VALUE) | |||||
return IXGBE_ERR_PHY; | |||||
return IXGBE_SUCCESS; | |||||
} | |||||
/** | |||||
* ixgbe_read_pe - Read register from port expander | * ixgbe_read_pe - Read register from port expander | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @reg: register number to read | * @reg: register number to read | ||||
* @value: pointer to receive read value | * @value: pointer to receive read value | ||||
* | * | ||||
* Returns status code | * Returns status code | ||||
**/ | **/ | ||||
static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) | static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) | ||||
Show All 25 Lines | ERROR_REPORT2(IXGBE_ERROR_CAUTION, | ||||
"port expander access failed with %d\n", status); | "port expander access failed with %d\n", status); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_reset_cs4227 - Reset CS4227 using port expander | * ixgbe_reset_cs4227 - Reset CS4227 using port expander | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
* This function assumes that the caller has acquired the proper semaphore. | |||||
* Returns error code | * Returns error code | ||||
**/ | **/ | ||||
static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) | static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) | ||||
{ | { | ||||
s32 status; | s32 status; | ||||
u32 retry; | |||||
u16 value; | |||||
u8 reg; | u8 reg; | ||||
/* Trigger hard reset. */ | |||||
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); | status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
reg |= IXGBE_PE_BIT1; | reg |= IXGBE_PE_BIT1; | ||||
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); | status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
Show All 18 Lines | static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) | ||||
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); | status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
reg |= IXGBE_PE_BIT1; | reg |= IXGBE_PE_BIT1; | ||||
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); | status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
/* Wait for the reset to complete. */ | |||||
msec_delay(IXGBE_CS4227_RESET_DELAY); | msec_delay(IXGBE_CS4227_RESET_DELAY); | ||||
for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { | |||||
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, | |||||
&value); | |||||
if (status == IXGBE_SUCCESS && | |||||
value == IXGBE_CS4227_EEPROM_LOAD_OK) | |||||
break; | |||||
msec_delay(IXGBE_CS4227_CHECK_DELAY); | |||||
} | |||||
if (retry == IXGBE_CS4227_RETRIES) { | |||||
ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, | |||||
"CS4227 reset did not complete."); | |||||
return IXGBE_ERR_PHY; | |||||
} | |||||
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); | |||||
if (status != IXGBE_SUCCESS || | |||||
!(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { | |||||
ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, | |||||
"CS4227 EEPROM did not load successfully."); | |||||
return IXGBE_ERR_PHY; | |||||
} | |||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_check_cs4227 - Check CS4227 and reset as needed | * ixgbe_check_cs4227 - Check CS4227 and reset as needed | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
**/ | **/ | ||||
static void ixgbe_check_cs4227(struct ixgbe_hw *hw) | static void ixgbe_check_cs4227(struct ixgbe_hw *hw) | ||||
{ | { | ||||
s32 status = IXGBE_SUCCESS; | |||||
u32 swfw_mask = hw->phy.phy_semaphore_mask; | u32 swfw_mask = hw->phy.phy_semaphore_mask; | ||||
s32 status; | u16 value = 0; | ||||
u8 retry; | u8 retry; | ||||
for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { | for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { | ||||
status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); | status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); | ||||
if (status != IXGBE_SUCCESS) { | if (status != IXGBE_SUCCESS) { | ||||
ERROR_REPORT2(IXGBE_ERROR_CAUTION, | ERROR_REPORT2(IXGBE_ERROR_CAUTION, | ||||
"semaphore failed with %d\n", status); | "semaphore failed with %d", status); | ||||
msec_delay(IXGBE_CS4227_CHECK_DELAY); | |||||
continue; | |||||
} | |||||
/* Get status of reset flow. */ | |||||
status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); | |||||
if (status == IXGBE_SUCCESS && | |||||
value == IXGBE_CS4227_RESET_COMPLETE) | |||||
goto out; | |||||
if (status != IXGBE_SUCCESS || | |||||
value != IXGBE_CS4227_RESET_PENDING) | |||||
break; | |||||
/* Reset is pending. Wait and check again. */ | |||||
hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |||||
msec_delay(IXGBE_CS4227_CHECK_DELAY); | |||||
} | |||||
/* If still pending, assume other instance failed. */ | |||||
if (retry == IXGBE_CS4227_RETRIES) { | |||||
status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); | |||||
if (status != IXGBE_SUCCESS) { | |||||
ERROR_REPORT2(IXGBE_ERROR_CAUTION, | |||||
"semaphore failed with %d", status); | |||||
return; | return; | ||||
} | } | ||||
status = ixgbe_get_cs4227_status(hw); | } | ||||
if (status == IXGBE_SUCCESS) { | |||||
/* Reset the CS4227. */ | |||||
status = ixgbe_reset_cs4227(hw); | |||||
if (status != IXGBE_SUCCESS) { | |||||
ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, | |||||
"CS4227 reset failed: %d", status); | |||||
goto out; | |||||
} | |||||
/* Reset takes so long, temporarily release semaphore in case the | |||||
* other driver instance is waiting for the reset indication. | |||||
*/ | |||||
ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, | |||||
IXGBE_CS4227_RESET_PENDING); | |||||
hw->mac.ops.release_swfw_sync(hw, swfw_mask); | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | ||||
msec_delay(hw->eeprom.semaphore_delay); | msec_delay(10); | ||||
status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); | |||||
if (status != IXGBE_SUCCESS) { | |||||
ERROR_REPORT2(IXGBE_ERROR_CAUTION, | |||||
"semaphore failed with %d", status); | |||||
return; | return; | ||||
} | } | ||||
ixgbe_reset_cs4227(hw); | |||||
/* Record completion for next time. */ | |||||
status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, | |||||
IXGBE_CS4227_RESET_COMPLETE); | |||||
out: | |||||
hw->mac.ops.release_swfw_sync(hw, swfw_mask); | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | ||||
msec_delay(hw->eeprom.semaphore_delay); | msec_delay(hw->eeprom.semaphore_delay); | ||||
} | } | ||||
ERROR_REPORT2(IXGBE_ERROR_CAUTION, | |||||
"Unable to initialize CS4227, err=%d\n", status); | |||||
} | |||||
/** | /** | ||||
* ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control | * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
**/ | **/ | ||||
static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) | static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | ||||
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines | s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) | ||||
/* AUTOC register is not present in x550EM. */ | /* AUTOC register is not present in x550EM. */ | ||||
mac->ops.prot_autoc_read = NULL; | mac->ops.prot_autoc_read = NULL; | ||||
mac->ops.prot_autoc_write = NULL; | mac->ops.prot_autoc_write = NULL; | ||||
/* X550EM bus type is internal*/ | /* X550EM bus type is internal*/ | ||||
hw->bus.type = ixgbe_bus_type_internal; | hw->bus.type = ixgbe_bus_type_internal; | ||||
mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; | mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; | ||||
if (hw->mac.type == ixgbe_mac_X550EM_x) { | |||||
mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; | mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; | ||||
mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; | mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; | ||||
} | |||||
mac->ops.get_media_type = ixgbe_get_media_type_X550em; | mac->ops.get_media_type = ixgbe_get_media_type_X550em; | ||||
mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; | mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; | ||||
mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; | mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; | ||||
mac->ops.reset_hw = ixgbe_reset_hw_X550em; | mac->ops.reset_hw = ixgbe_reset_hw_X550em; | ||||
mac->ops.get_supported_physical_layer = | mac->ops.get_supported_physical_layer = | ||||
ixgbe_get_supported_physical_layer_X550em; | ixgbe_get_supported_physical_layer_X550em; | ||||
if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) | ||||
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines | s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) | ||||
DEBUGFUNC("ixgbe_setup_eee_X550"); | DEBUGFUNC("ixgbe_setup_eee_X550"); | ||||
eeer = IXGBE_READ_REG(hw, IXGBE_EEER); | eeer = IXGBE_READ_REG(hw, IXGBE_EEER); | ||||
/* Enable or disable EEE per flag */ | /* Enable or disable EEE per flag */ | ||||
if (enable_eee) { | if (enable_eee) { | ||||
eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); | eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); | ||||
if (hw->device_id == IXGBE_DEV_ID_X550T) { | if (hw->mac.type == ixgbe_mac_X550) { | ||||
/* Advertise EEE capability */ | /* Advertise EEE capability */ | ||||
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, | hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, | ||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); | ||||
autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | | autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | | ||||
IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | | IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | | ||||
IXGBE_AUTO_NEG_100BASE_EEE_ADVT); | IXGBE_AUTO_NEG_100BASE_EEE_ADVT); | ||||
Show All 21 Lines | if (hw->mac.type == ixgbe_mac_X550) { | ||||
IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | ||||
IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); | IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
} | } | ||||
} else { | } else { | ||||
eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); | eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); | ||||
if (hw->device_id == IXGBE_DEV_ID_X550T) { | if (hw->mac.type == ixgbe_mac_X550) { | ||||
/* Disable advertised EEE capability */ | /* Disable advertised EEE capability */ | ||||
hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, | hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, | ||||
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); | ||||
autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | | autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | | ||||
IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | | IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | | ||||
IXGBE_AUTO_NEG_100BASE_EEE_ADVT); | IXGBE_AUTO_NEG_100BASE_EEE_ADVT); | ||||
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines | |||||
* @ctrl: pointer to location to receive final IOSF control value | * @ctrl: pointer to location to receive final IOSF control value | ||||
* | * | ||||
* Returns failing status on timeout | * Returns failing status on timeout | ||||
* | * | ||||
* Note: ctrl can be NULL if the IOSF control register value is not needed | * Note: ctrl can be NULL if the IOSF control register value is not needed | ||||
**/ | **/ | ||||
static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) | static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) | ||||
{ | { | ||||
u32 i, command; | u32 i, command = 0; | ||||
/* Check every 10 usec to see if the address cycle completed. | /* Check every 10 usec to see if the address cycle completed. | ||||
* The SB IOSF BUSY bit will clear when the operation is | * The SB IOSF BUSY bit will clear when the operation is | ||||
* complete | * complete | ||||
*/ | */ | ||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | ||||
command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); | command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); | ||||
if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) | if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) | ||||
▲ Show 20 Lines • Show All 611 Lines • ▼ Show 20 Lines | static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, | ||||
status = ixgbe_read_iosf_sb_reg_x550(hw, | status = ixgbe_read_iosf_sb_reg_x550(hw, | ||||
IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | ||||
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | ||||
if (status) | if (status) | ||||
return status; | return status; | ||||
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; | ||||
reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | | |||||
IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); | |||||
reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | | reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | | ||||
IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); | IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); | ||||
/* Advertise 10G support. */ | /* Advertise 10G support. */ | ||||
if (speed & IXGBE_LINK_SPEED_10GB_FULL) | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | ||||
reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; | ||||
/* Advertise 1G support. */ | /* Advertise 1G support. */ | ||||
Show All 30 Lines | s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) | ||||
if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { | if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { | ||||
phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | ||||
ixgbe_setup_mux_ctl(hw); | ixgbe_setup_mux_ctl(hw); | ||||
/* Save NW management interface connected on board. This is used | /* Save NW management interface connected on board. This is used | ||||
* to determine internal PHY mode. | * to determine internal PHY mode. | ||||
*/ | */ | ||||
phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); | phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); | ||||
/* If internal PHY mode is KR, then initialize KR link */ | |||||
if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { | if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { | ||||
speed = IXGBE_LINK_SPEED_10GB_FULL | | speed = IXGBE_LINK_SPEED_10GB_FULL | | ||||
IXGBE_LINK_SPEED_1GB_FULL; | IXGBE_LINK_SPEED_1GB_FULL; | ||||
ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); | |||||
} | } | ||||
phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; | phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; | ||||
} | } | ||||
/* Identify the PHY or SFP module */ | /* Identify the PHY or SFP module */ | ||||
ret_val = phy->ops.identify(hw); | ret_val = phy->ops.identify(hw); | ||||
if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) | if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) | ||||
return ret_val; | return ret_val; | ||||
/* Setup function pointers based on detected hardware */ | /* Setup function pointers based on detected hardware */ | ||||
ixgbe_init_mac_link_ops_X550em(hw); | ixgbe_init_mac_link_ops_X550em(hw); | ||||
if (phy->sfp_type != ixgbe_sfp_type_unknown) | if (phy->sfp_type != ixgbe_sfp_type_unknown) | ||||
phy->ops.reset = NULL; | phy->ops.reset = NULL; | ||||
/* Set functions pointers based on phy type */ | /* Set functions pointers based on phy type */ | ||||
switch (hw->phy.type) { | switch (hw->phy.type) { | ||||
case ixgbe_phy_x550em_kx4: | case ixgbe_phy_x550em_kx4: | ||||
phy->ops.setup_link = ixgbe_setup_kx4_x550em; | phy->ops.setup_link = NULL; | ||||
phy->ops.read_reg = ixgbe_read_phy_reg_x550em; | phy->ops.read_reg = ixgbe_read_phy_reg_x550em; | ||||
phy->ops.write_reg = ixgbe_write_phy_reg_x550em; | phy->ops.write_reg = ixgbe_write_phy_reg_x550em; | ||||
break; | break; | ||||
case ixgbe_phy_x550em_kr: | case ixgbe_phy_x550em_kr: | ||||
phy->ops.setup_link = ixgbe_setup_kr_x550em; | phy->ops.setup_link = ixgbe_setup_kr_x550em; | ||||
phy->ops.read_reg = ixgbe_read_phy_reg_x550em; | phy->ops.read_reg = ixgbe_read_phy_reg_x550em; | ||||
phy->ops.write_reg = ixgbe_write_phy_reg_x550em; | phy->ops.write_reg = ixgbe_write_phy_reg_x550em; | ||||
break; | break; | ||||
Show All 10 Lines | if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { | ||||
phy->ops.setup_internal_link = | phy->ops.setup_internal_link = | ||||
ixgbe_setup_internal_phy_t_x550em; | ixgbe_setup_internal_phy_t_x550em; | ||||
} else { | } else { | ||||
speed = IXGBE_LINK_SPEED_10GB_FULL | | speed = IXGBE_LINK_SPEED_10GB_FULL | | ||||
IXGBE_LINK_SPEED_1GB_FULL; | IXGBE_LINK_SPEED_1GB_FULL; | ||||
ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); | ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); | ||||
} | } | ||||
/* setup SW LPLU only for first revision */ | |||||
if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, | |||||
IXGBE_FUSES0_GROUP(0)))) | |||||
phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; | phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; | ||||
phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; | phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; | ||||
phy->ops.reset = ixgbe_reset_phy_t_X550em; | phy->ops.reset = ixgbe_reset_phy_t_X550em; | ||||
break; | break; | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
return ret_val; | return ret_val; | ||||
} | } | ||||
Show All 20 Lines | s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) | ||||
/* Call adapter stop to disable Tx/Rx and clear interrupts */ | /* Call adapter stop to disable Tx/Rx and clear interrupts */ | ||||
status = hw->mac.ops.stop_adapter(hw); | status = hw->mac.ops.stop_adapter(hw); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
/* flush pending Tx transactions */ | /* flush pending Tx transactions */ | ||||
ixgbe_clear_tx_pending(hw); | ixgbe_clear_tx_pending(hw); | ||||
/* PHY ops must be identified and initialized prior to reset */ | if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { | ||||
/* Config MDIO clock speed before the first MDIO PHY access */ | |||||
hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |||||
hlreg0 &= ~IXGBE_HLREG0_MDCSPD; | |||||
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |||||
} | |||||
/* Identify PHY and related function pointers */ | /* PHY ops must be identified and initialized prior to reset */ | ||||
status = hw->phy.ops.init(hw); | status = hw->phy.ops.init(hw); | ||||
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) | ||||
return status; | return status; | ||||
/* start the external PHY */ | /* start the external PHY */ | ||||
if (hw->phy.type == ixgbe_phy_x550em_ext_t) { | if (hw->phy.type == ixgbe_phy_x550em_ext_t) { | ||||
status = ixgbe_init_ext_t_x550em(hw); | status = ixgbe_init_ext_t_x550em(hw); | ||||
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines | mac_reset_top: | ||||
/* Store MAC address from RAR0, clear receive address registers, and | /* Store MAC address from RAR0, clear receive address registers, and | ||||
* clear the multicast table. Also reset num_rar_entries to 128, | * clear the multicast table. Also reset num_rar_entries to 128, | ||||
* since we modify this value when programming the SAN MAC address. | * since we modify this value when programming the SAN MAC address. | ||||
*/ | */ | ||||
hw->mac.num_rar_entries = 128; | hw->mac.num_rar_entries = 128; | ||||
hw->mac.ops.init_rx_addrs(hw); | hw->mac.ops.init_rx_addrs(hw); | ||||
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { | |||||
/* Config MDIO clock speed. */ | |||||
hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |||||
hlreg0 &= ~IXGBE_HLREG0_MDCSPD; | |||||
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |||||
} | |||||
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) | if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) | ||||
ixgbe_setup_mux_ctl(hw); | ixgbe_setup_mux_ctl(hw); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. | * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. | ||||
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines | |||||
* Configures the integrated KR PHY. | * Configures the integrated KR PHY. | ||||
**/ | **/ | ||||
s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) | s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) | ||||
{ | { | ||||
return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); | return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_setup_kx4_x550em - Configure the KX4 PHY. | |||||
* @hw: pointer to hardware structure | |||||
* | |||||
* Configures the integrated KX4 PHY. | |||||
**/ | |||||
s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) | |||||
{ | |||||
s32 status; | |||||
u32 reg_val; | |||||
status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, | |||||
IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val); | |||||
if (status) | |||||
return status; | |||||
reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | | |||||
IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); | |||||
reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; | |||||
/* Advertise 10G support. */ | |||||
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) | |||||
reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; | |||||
/* Advertise 1G support. */ | |||||
if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | |||||
reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; | |||||
/* Restart auto-negotiation. */ | |||||
reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; | |||||
status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, | |||||
IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val); | |||||
return status; | |||||
} | |||||
/** | |||||
* ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP | * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
* Configure the external PHY and the integrated KR PHY for SFP support. | * Configure the external PHY and the integrated KR PHY for SFP support. | ||||
**/ | **/ | ||||
s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, | s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, | ||||
ixgbe_link_speed speed, | ixgbe_link_speed speed, | ||||
bool autoneg_wait_to_complete) | bool autoneg_wait_to_complete) | ||||
Show All 11 Lines | s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, | ||||
* not excepted in the setup MAC link flow. | * not excepted in the setup MAC link flow. | ||||
*/ | */ | ||||
if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) | if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) | ||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
if (ret_val != IXGBE_SUCCESS) | if (ret_val != IXGBE_SUCCESS) | ||||
return ret_val; | return ret_val; | ||||
/* Configure CS4227 for LINE connection rate then type. */ | if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { | ||||
reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12); | /* Configure CS4227 LINE side to 10G SR. */ | ||||
reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; | reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + | ||||
(hw->bus.lan_id << 12); | |||||
reg_val = IXGBE_CS4227_SPEED_10G; | |||||
ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ||||
reg_val); | reg_val); | ||||
reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); | reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + | ||||
if (setup_linear) | (hw->bus.lan_id << 12); | ||||
reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | |||||
else | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | ||||
ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ||||
reg_val); | reg_val); | ||||
/* Configure CS4227 for HOST connection rate then type. */ | /* Configure CS4227 for HOST connection rate then type. */ | ||||
reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12); | reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + | ||||
reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; | (hw->bus.lan_id << 12); | ||||
reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? | |||||
IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G; | |||||
ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ||||
reg_val); | reg_val); | ||||
reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12); | reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + | ||||
(hw->bus.lan_id << 12); | |||||
if (setup_linear) | if (setup_linear) | ||||
reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | ||||
else | else | ||||
reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | ||||
ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | ||||
reg_val); | reg_val); | ||||
/* If internal link mode is XFI, then setup XFI internal link. */ | /* Setup XFI internal link. */ | ||||
if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) | |||||
ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); | ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); | ||||
} else { | |||||
/* Configure internal PHY for KR/KX. */ | |||||
ixgbe_setup_kr_speed_x550em(hw, speed); | |||||
/* Configure CS4227 LINE side to proper mode. */ | |||||
reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + | |||||
(hw->bus.lan_id << 12); | |||||
if (setup_linear) | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | |||||
else | |||||
reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | |||||
ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | |||||
reg_val); | |||||
} | |||||
return ret_val; | return ret_val; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. | * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @speed: the link speed to force | * @speed: the link speed to force | ||||
* | * | ||||
▲ Show 20 Lines • Show All 904 Lines • ▼ Show 20 Lines | |||||
s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) | s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u16 an_10g_cntl_reg, autoneg_reg, speed; | u16 an_10g_cntl_reg, autoneg_reg, speed; | ||||
s32 status; | s32 status; | ||||
ixgbe_link_speed lcd_speed; | ixgbe_link_speed lcd_speed; | ||||
u32 save_autoneg; | u32 save_autoneg; | ||||
bool link_up; | bool link_up; | ||||
/* SW LPLU not required on later HW revisions. */ | |||||
if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))) | |||||
return IXGBE_SUCCESS; | |||||
/* If blocked by MNG FW, then don't restart AN */ | /* If blocked by MNG FW, then don't restart AN */ | ||||
if (ixgbe_check_reset_blocked(hw)) | if (ixgbe_check_reset_blocked(hw)) | ||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); | status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); | ||||
if (status != IXGBE_SUCCESS) | if (status != IXGBE_SUCCESS) | ||||
return status; | return status; | ||||
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines | case ixgbe_fc_full: | ||||
break; | break; | ||||
default: | default: | ||||
ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, | ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, | ||||
"Flow control param set incorrectly\n"); | "Flow control param set incorrectly\n"); | ||||
ret_val = IXGBE_ERR_CONFIG; | ret_val = IXGBE_ERR_CONFIG; | ||||
goto out; | goto out; | ||||
} | } | ||||
if (hw->phy.media_type == ixgbe_media_type_backplane) { | if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { | ||||
ret_val = ixgbe_read_iosf_sb_reg_x550(hw, | ret_val = ixgbe_read_iosf_sb_reg_x550(hw, | ||||
IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), | IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), | ||||
IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | ||||
if (ret_val != IXGBE_SUCCESS) | if (ret_val != IXGBE_SUCCESS) | ||||
goto out; | goto out; | ||||
reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | | reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | | ||||
IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); | IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); | ||||
if (pause) | if (pause) | ||||
reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; | reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; | ||||
if (asm_dir) | if (asm_dir) | ||||
reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; | reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; | ||||
ret_val = ixgbe_write_iosf_sb_reg_x550(hw, | ret_val = ixgbe_write_iosf_sb_reg_x550(hw, | ||||
IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), | IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), | ||||
IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | ||||
/* Not all devices fully support AN. */ | /* This device does not fully support AN. */ | ||||
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) | |||||
hw->fc.disable_fc_autoneg = TRUE; | hw->fc.disable_fc_autoneg = TRUE; | ||||
} | } | ||||
out: | out: | ||||
return ret_val; | return ret_val; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_set_mux - Set mux for port 1 access with CS4227 | * ixgbe_set_mux - Set mux for port 1 access with CS4227 | ||||
▲ Show 20 Lines • Show All 238 Lines • Show Last 20 Lines |