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stable/10/sys/dev/ixgbe/ixgbe_x540.c
Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines | s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) | ||||
mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | ||||
mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); | ||||
/* | /* | ||||
* FWSM register | * FWSM register | ||||
* ARC supported; valid only if manageability features are | * ARC supported; valid only if manageability features are | ||||
* enabled. | * enabled. | ||||
*/ | */ | ||||
mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & | mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) | ||||
IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; | & IXGBE_FWSM_MODE_MASK); | ||||
hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; | hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; | ||||
/* LEDs */ | /* LEDs */ | ||||
mac->ops.blink_led_start = ixgbe_blink_led_start_X540; | mac->ops.blink_led_start = ixgbe_blink_led_start_X540; | ||||
mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; | mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; | ||||
/* Manageability interface */ | /* Manageability interface */ | ||||
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines | s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) | ||||
u16 eeprom_size; | u16 eeprom_size; | ||||
DEBUGFUNC("ixgbe_init_eeprom_params_X540"); | DEBUGFUNC("ixgbe_init_eeprom_params_X540"); | ||||
if (eeprom->type == ixgbe_eeprom_uninitialized) { | if (eeprom->type == ixgbe_eeprom_uninitialized) { | ||||
eeprom->semaphore_delay = 10; | eeprom->semaphore_delay = 10; | ||||
eeprom->type = ixgbe_flash; | eeprom->type = ixgbe_flash; | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | ||||
IXGBE_EEC_SIZE_SHIFT); | IXGBE_EEC_SIZE_SHIFT); | ||||
eeprom->word_size = 1 << (eeprom_size + | eeprom->word_size = 1 << (eeprom_size + | ||||
IXGBE_EEPROM_WORD_SIZE_SHIFT); | IXGBE_EEPROM_WORD_SIZE_SHIFT); | ||||
DEBUGOUT2("Eeprom params: type = %d, size = %d\n", | DEBUGOUT2("Eeprom params: type = %d, size = %d\n", | ||||
eeprom->type, eeprom->word_size); | eeprom->type, eeprom->word_size); | ||||
} | } | ||||
▲ Show 20 Lines • Show All 308 Lines • ▼ Show 20 Lines | s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) | ||||
DEBUGFUNC("ixgbe_update_flash_X540"); | DEBUGFUNC("ixgbe_update_flash_X540"); | ||||
status = ixgbe_poll_flash_update_done_X540(hw); | status = ixgbe_poll_flash_update_done_X540(hw); | ||||
if (status == IXGBE_ERR_EEPROM) { | if (status == IXGBE_ERR_EEPROM) { | ||||
DEBUGOUT("Flash update time out\n"); | DEBUGOUT("Flash update time out\n"); | ||||
goto out; | goto out; | ||||
} | } | ||||
flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; | flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); | ||||
status = ixgbe_poll_flash_update_done_X540(hw); | status = ixgbe_poll_flash_update_done_X540(hw); | ||||
if (status == IXGBE_SUCCESS) | if (status == IXGBE_SUCCESS) | ||||
DEBUGOUT("Flash update complete\n"); | DEBUGOUT("Flash update complete\n"); | ||||
else | else | ||||
DEBUGOUT("Flash update time out\n"); | DEBUGOUT("Flash update time out\n"); | ||||
if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { | if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { | ||||
flup = IXGBE_READ_REG(hw, IXGBE_EEC); | flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
if (flup & IXGBE_EEC_SEC1VAL) { | if (flup & IXGBE_EEC_SEC1VAL) { | ||||
flup |= IXGBE_EEC_FLUP; | flup |= IXGBE_EEC_FLUP; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); | ||||
} | } | ||||
status = ixgbe_poll_flash_update_done_X540(hw); | status = ixgbe_poll_flash_update_done_X540(hw); | ||||
if (status == IXGBE_SUCCESS) | if (status == IXGBE_SUCCESS) | ||||
DEBUGOUT("Flash update complete\n"); | DEBUGOUT("Flash update complete\n"); | ||||
else | else | ||||
DEBUGOUT("Flash update time out\n"); | DEBUGOUT("Flash update time out\n"); | ||||
} | } | ||||
Show All 12 Lines | |||||
{ | { | ||||
u32 i; | u32 i; | ||||
u32 reg; | u32 reg; | ||||
s32 status = IXGBE_ERR_EEPROM; | s32 status = IXGBE_ERR_EEPROM; | ||||
DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); | DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); | ||||
for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { | for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { | ||||
reg = IXGBE_READ_REG(hw, IXGBE_EEC); | reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
if (reg & IXGBE_EEC_FLUDONE) { | if (reg & IXGBE_EEC_FLUDONE) { | ||||
status = IXGBE_SUCCESS; | status = IXGBE_SUCCESS; | ||||
break; | break; | ||||
} | } | ||||
msec_delay(5); | msec_delay(5); | ||||
} | } | ||||
if (i == IXGBE_FLUDONE_ATTEMPTS) | if (i == IXGBE_FLUDONE_ATTEMPTS) | ||||
Show All 34 Lines | s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) | ||||
fwmask |= swi2c_mask << 2; | fwmask |= swi2c_mask << 2; | ||||
for (i = 0; i < timeout; i++) { | for (i = 0; i < timeout; i++) { | ||||
/* SW NVM semaphore bit is used for access to all | /* SW NVM semaphore bit is used for access to all | ||||
* SW_FW_SYNC bits (not just NVM) | * SW_FW_SYNC bits (not just NVM) | ||||
*/ | */ | ||||
if (ixgbe_get_swfw_sync_semaphore(hw)) | if (ixgbe_get_swfw_sync_semaphore(hw)) | ||||
return IXGBE_ERR_SWFW_SYNC; | return IXGBE_ERR_SWFW_SYNC; | ||||
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
if (!(swfw_sync & (fwmask | swmask | hwmask))) { | if (!(swfw_sync & (fwmask | swmask | hwmask))) { | ||||
swfw_sync |= swmask; | swfw_sync |= swmask; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), | ||||
swfw_sync); | |||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | msec_delay(5); | ||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
/* Firmware currently using resource (fwmask), hardware | /* Firmware currently using resource (fwmask), hardware | ||||
* currently using resource (hwmask), or other software | * currently using resource (hwmask), or other software | ||||
* thread currently using resource (swmask) | * thread currently using resource (swmask) | ||||
*/ | */ | ||||
Show All 10 Lines | s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) | ||||
/* If the resource is not released by the FW/HW the SW can assume that | /* If the resource is not released by the FW/HW the SW can assume that | ||||
* the FW/HW malfunctions. In that case the SW should set the SW bit(s) | * the FW/HW malfunctions. In that case the SW should set the SW bit(s) | ||||
* of the requested resource(s) while ignoring the corresponding FW/HW | * of the requested resource(s) while ignoring the corresponding FW/HW | ||||
* bits in the SW_FW_SYNC register. | * bits in the SW_FW_SYNC register. | ||||
*/ | */ | ||||
if (ixgbe_get_swfw_sync_semaphore(hw)) | if (ixgbe_get_swfw_sync_semaphore(hw)) | ||||
return IXGBE_ERR_SWFW_SYNC; | return IXGBE_ERR_SWFW_SYNC; | ||||
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
if (swfw_sync & (fwmask | hwmask)) { | if (swfw_sync & (fwmask | hwmask)) { | ||||
swfw_sync |= swmask; | swfw_sync |= swmask; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); | ||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | msec_delay(5); | ||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
/* If the resource is not released by other SW the SW can assume that | /* If the resource is not released by other SW the SW can assume that | ||||
* the other SW malfunctions. In that case the SW should clear all SW | * the other SW malfunctions. In that case the SW should clear all SW | ||||
* flags that it does not own and then repeat the whole process once | * flags that it does not own and then repeat the whole process once | ||||
* again. | * again. | ||||
Show All 27 Lines | void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) | ||||
u32 swfw_sync; | u32 swfw_sync; | ||||
DEBUGFUNC("ixgbe_release_swfw_sync_X540"); | DEBUGFUNC("ixgbe_release_swfw_sync_X540"); | ||||
if (mask & IXGBE_GSSR_I2C_MASK) | if (mask & IXGBE_GSSR_I2C_MASK) | ||||
swmask |= mask & IXGBE_GSSR_I2C_MASK; | swmask |= mask & IXGBE_GSSR_I2C_MASK; | ||||
ixgbe_get_swfw_sync_semaphore(hw); | ixgbe_get_swfw_sync_semaphore(hw); | ||||
swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
swfw_sync &= ~swmask; | swfw_sync &= ~swmask; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); | ||||
ixgbe_release_swfw_sync_semaphore(hw); | ixgbe_release_swfw_sync_semaphore(hw); | ||||
msec_delay(5); | msec_delay(5); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_get_swfw_sync_semaphore - Get hardware semaphore | * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
Show All 10 Lines | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) | ||||
DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); | DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); | ||||
/* Get SMBI software semaphore between device drivers first */ | /* Get SMBI software semaphore between device drivers first */ | ||||
for (i = 0; i < timeout; i++) { | for (i = 0; i < timeout; i++) { | ||||
/* | /* | ||||
* If the SMBI bit is 0 when we read it, then the bit will be | * If the SMBI bit is 0 when we read it, then the bit will be | ||||
* set and we have the semaphore | * set and we have the semaphore | ||||
*/ | */ | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
if (!(swsm & IXGBE_SWSM_SMBI)) { | if (!(swsm & IXGBE_SWSM_SMBI)) { | ||||
status = IXGBE_SUCCESS; | status = IXGBE_SUCCESS; | ||||
break; | break; | ||||
} | } | ||||
usec_delay(50); | usec_delay(50); | ||||
} | } | ||||
/* Now get the semaphore between SW/FW through the REGSMP bit */ | /* Now get the semaphore between SW/FW through the REGSMP bit */ | ||||
if (status == IXGBE_SUCCESS) { | if (status == IXGBE_SUCCESS) { | ||||
for (i = 0; i < timeout; i++) { | for (i = 0; i < timeout; i++) { | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
if (!(swsm & IXGBE_SWFW_REGSMP)) | if (!(swsm & IXGBE_SWFW_REGSMP)) | ||||
break; | break; | ||||
usec_delay(50); | usec_delay(50); | ||||
} | } | ||||
/* | /* | ||||
* Release semaphores and return error if SW NVM semaphore | * Release semaphores and return error if SW NVM semaphore | ||||
Show All 23 Lines | |||||
static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 swsm; | u32 swsm; | ||||
DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); | DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); | ||||
/* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ | /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); | ||||
swsm &= ~IXGBE_SWFW_REGSMP; | swsm &= ~IXGBE_SWFW_REGSMP; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
swsm &= ~IXGBE_SWSM_SMBI; | swsm &= ~IXGBE_SWSM_SMBI; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_blink_led_start_X540 - Blink LED based on index. | * ixgbe_blink_led_start_X540 - Blink LED based on index. | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @index: led number to blink | * @index: led number to blink | ||||
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines |