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Differential D5117 Diff 13233 stable/10/sys/dev/ixgbe/ixgbe_type.h

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stable/10/sys/dev/ixgbe/ixgbe_type.h

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#define IXGBE_DEV_ID_82599_VF_HV 0x152E #define IXGBE_DEV_ID_82599_VF_HV 0x152E
#define IXGBE_DEV_ID_82599_BYPASS 0x155D #define IXGBE_DEV_ID_82599_BYPASS 0x155D
#define IXGBE_DEV_ID_X540T 0x1528 #define IXGBE_DEV_ID_X540T 0x1528
#define IXGBE_DEV_ID_X540_VF 0x1515 #define IXGBE_DEV_ID_X540_VF 0x1515
#define IXGBE_DEV_ID_X540_VF_HV 0x1530 #define IXGBE_DEV_ID_X540_VF_HV 0x1530
#define IXGBE_DEV_ID_X540_BYPASS 0x155C #define IXGBE_DEV_ID_X540_BYPASS 0x155C
#define IXGBE_DEV_ID_X540T1 0x1560 #define IXGBE_DEV_ID_X540T1 0x1560
#define IXGBE_DEV_ID_X550T 0x1563 #define IXGBE_DEV_ID_X550T 0x1563
#define IXGBE_DEV_ID_X550T1 0x15D1
#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
#define IXGBE_DEV_ID_X550_VF_HV 0x1564 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
#define IXGBE_DEV_ID_X550_VF 0x1565 #define IXGBE_DEV_ID_X550_VF 0x1565
#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
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#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
#define IXGBE_MAX_PHY_ADDR 32 #define IXGBE_MAX_PHY_ADDR 32
/* PHY IDs*/ /* PHY IDs*/
#define TN1010_PHY_ID 0x00A19410 #define TN1010_PHY_ID 0x00A19410
#define TNX_FW_REV 0xB #define TNX_FW_REV 0xB
#define X540_PHY_ID 0x01540200 #define X540_PHY_ID 0x01540200
#define X550_PHY_ID 0x01540220 #define X550_PHY_ID1 0x01540220
#define X550_PHY_ID2 0x01540223
#define X550_PHY_ID3 0x01540221
#define X557_PHY_ID 0x01540240 #define X557_PHY_ID 0x01540240
#define AQ_FW_REV 0x20 #define AQ_FW_REV 0x20
#define QT2022_PHY_ID 0x0043A400 #define QT2022_PHY_ID 0x0043A400
#define ATH_PHY_ID 0x03429050 #define ATH_PHY_ID 0x03429050
/* PHY Types */ /* PHY Types */
#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
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* *
* Current filters: * Current filters:
* EAPOL 802.1x (0x888e): Filter 0 * EAPOL 802.1x (0x888e): Filter 0
* FCoE (0x8906): Filter 2 * FCoE (0x8906): Filter 2
* 1588 (0x88f7): Filter 3 * 1588 (0x88f7): Filter 3
* FIP (0x8914): Filter 4 * FIP (0x8914): Filter 4
* LLDP (0x88CC): Filter 5 * LLDP (0x88CC): Filter 5
* LACP (0x8809): Filter 6 * LACP (0x8809): Filter 6
* FC (0x8808): Filter 7
*/ */
#define IXGBE_ETQF_FILTER_EAPOL 0 #define IXGBE_ETQF_FILTER_EAPOL 0
#define IXGBE_ETQF_FILTER_FCOE 2 #define IXGBE_ETQF_FILTER_FCOE 2
#define IXGBE_ETQF_FILTER_1588 3 #define IXGBE_ETQF_FILTER_1588 3
#define IXGBE_ETQF_FILTER_FIP 4 #define IXGBE_ETQF_FILTER_FIP 4
#define IXGBE_ETQF_FILTER_LLDP 5 #define IXGBE_ETQF_FILTER_LLDP 5
#define IXGBE_ETQF_FILTER_LACP 6 #define IXGBE_ETQF_FILTER_LACP 6
#define IXGBE_ETQF_FILTER_FC 7
/* VLAN Control Bit Masks */ /* VLAN Control Bit Masks */
#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
/* VLAN pool filtering masks */ /* VLAN pool filtering masks */
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#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
#define IXGBE_FDIRCTRL_DROP_Q_MASK 0x00007F00
#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
#define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000
#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */ #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */
#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */ #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */
#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
#define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000 #define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000
#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
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#define FW_SHADOW_RAM_DUMP_CMD 0x36 #define FW_SHADOW_RAM_DUMP_CMD 0x36
#define FW_SHADOW_RAM_DUMP_LEN 0 #define FW_SHADOW_RAM_DUMP_LEN 0
#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
#define FW_NVM_DATA_OFFSET 3 #define FW_NVM_DATA_OFFSET 3
#define FW_MAX_READ_BUFFER_SIZE 1024 #define FW_MAX_READ_BUFFER_SIZE 1024
#define FW_DISABLE_RXEN_CMD 0xDE #define FW_DISABLE_RXEN_CMD 0xDE
#define FW_DISABLE_RXEN_LEN 0x1 #define FW_DISABLE_RXEN_LEN 0x1
#define FW_PHY_MGMT_REQ_CMD 0x20 #define FW_PHY_MGMT_REQ_CMD 0x20
#define FW_INT_PHY_REQ_CMD 0xB
#define FW_INT_PHY_REQ_LEN 10
#define FW_INT_PHY_REQ_READ 0
#define FW_INT_PHY_REQ_WRITE 1
/* Host Interface Command Structures */ /* Host Interface Command Structures */
struct ixgbe_hic_hdr { struct ixgbe_hic_hdr {
u8 cmd; u8 cmd;
u8 buf_len; u8 buf_len;
union { union {
u8 cmd_resv; u8 cmd_resv;
u8 ret_status; u8 ret_status;
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struct ixgbe_hic_disable_rxen { struct ixgbe_hic_disable_rxen {
struct ixgbe_hic_hdr hdr; struct ixgbe_hic_hdr hdr;
u8 port_number; u8 port_number;
u8 pad2; u8 pad2;
u16 pad3; u16 pad3;
}; };
struct ixgbe_hic_internal_phy_req {
struct ixgbe_hic_hdr hdr;
u8 port_number;
u8 command_type;
u16 address;
u16 rsv1;
u32 write_data;
u16 pad;
};
struct ixgbe_hic_internal_phy_resp {
struct ixgbe_hic_hdr hdr;
u32 read_data;
};
/* Transmit Descriptor - Legacy */ /* Transmit Descriptor - Legacy */
struct ixgbe_legacy_tx_desc { struct ixgbe_legacy_tx_desc {
u64 buffer_addr; /* Address of the descriptor's data buffer */ u64 buffer_addr; /* Address of the descriptor's data buffer */
union { union {
__le32 data; __le32 data;
struct { struct {
__le16 length; /* Data buffer length */ __le16 length; /* Data buffer length */
u8 cso; /* Checksum offset */ u8 cso; /* Checksum offset */
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#define IXGBE_MVALS_INIT(m) \ #define IXGBE_MVALS_INIT(m) \
IXGBE_CAT(EEC, m), \ IXGBE_CAT(EEC, m), \
IXGBE_CAT(FLA, m), \ IXGBE_CAT(FLA, m), \
IXGBE_CAT(GRC, m), \ IXGBE_CAT(GRC, m), \
IXGBE_CAT(SRAMREL, m), \ IXGBE_CAT(SRAMREL, m), \
IXGBE_CAT(FACTPS, m), \ IXGBE_CAT(FACTPS, m), \
IXGBE_CAT(SWSM, m), \ IXGBE_CAT(SWSM, m), \
IXGBE_CAT(SWFW_SYNC, m), \
IXGBE_CAT(FWSM, m), \ IXGBE_CAT(FWSM, m), \
IXGBE_CAT(SDP0_GPIEN, m), \ IXGBE_CAT(SDP0_GPIEN, m), \
IXGBE_CAT(SDP1_GPIEN, m), \ IXGBE_CAT(SDP1_GPIEN, m), \
IXGBE_CAT(SDP2_GPIEN, m), \ IXGBE_CAT(SDP2_GPIEN, m), \
IXGBE_CAT(EICR_GPI_SDP0, m), \ IXGBE_CAT(EICR_GPI_SDP0, m), \
IXGBE_CAT(EICR_GPI_SDP1, m), \ IXGBE_CAT(EICR_GPI_SDP1, m), \
IXGBE_CAT(EICR_GPI_SDP2, m), \ IXGBE_CAT(EICR_GPI_SDP2, m), \
IXGBE_CAT(CIAA, m), \ IXGBE_CAT(CIAA, m), \
▲ Show 20 Lines • Show All 466 Lines • ▼ Show 20 Lines#define IXGBE_MAX_MTA 128
u32 orig_autoc2; u32 orig_autoc2;
u16 max_msix_vectors; u16 max_msix_vectors;
bool arc_subsystem_valid; bool arc_subsystem_valid;
bool orig_link_settings_stored; bool orig_link_settings_stored;
bool autotry_restart; bool autotry_restart;
u8 flags; u8 flags;
struct ixgbe_dmac_config dmac_config; struct ixgbe_dmac_config dmac_config;
bool set_lben; bool set_lben;
u32 max_link_up_time;
}; };
struct ixgbe_phy_info { struct ixgbe_phy_info {
struct ixgbe_phy_operations ops; struct ixgbe_phy_operations ops;
enum ixgbe_phy_type type; enum ixgbe_phy_type type;
u32 addr; u32 addr;
u32 id; u32 id;
enum ixgbe_sfp_type sfp_type; enum ixgbe_sfp_type sfp_type;
bool sfp_setup_needed; bool sfp_setup_needed;
u32 revision; u32 revision;
enum ixgbe_media_type media_type; enum ixgbe_media_type media_type;
u32 phy_semaphore_mask; u32 phy_semaphore_mask;
bool reset_disable; bool reset_disable;
ixgbe_autoneg_advertised autoneg_advertised; ixgbe_autoneg_advertised autoneg_advertised;
ixgbe_link_speed speeds_supported;
enum ixgbe_smart_speed smart_speed; enum ixgbe_smart_speed smart_speed;
bool smart_speed_active; bool smart_speed_active;
bool multispeed_fiber; bool multispeed_fiber;
bool reset_if_overtemp; bool reset_if_overtemp;
bool qsfp_shared_i2c_bus; bool qsfp_shared_i2c_bus;
u32 nw_mng_if_sel; u32 nw_mng_if_sel;
}; };
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#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
#define IXGBE_FUSES0_300MHZ (1 << 5) #define IXGBE_FUSES0_300MHZ (1 << 5)
#define IXGBE_FUSES0_REV1 (1 << 6) #define IXGBE_FUSES0_REV1 (1 << 6)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P == 0) ? (0x4010) : (0x8010)) #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
#define IXGBE_KRM_LINK_CTRL_1(P) ((P == 0) ? (0x420C) : (0x820C)) #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
#define IXGBE_KRM_AN_CNTL_1(P) ((P == 0) ? (0x422C) : (0x822C)) #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P == 0) ? (0x4634) : (0x8634)) #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P == 0) ? (0x4638) : (0x8638)) #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P == 0) ? (0x4B00) : (0x8B00)) #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P == 0) ? (0x4E00) : (0x8E00)) #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P == 0) ? (0x5520) : (0x9520)) #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
#define IXGBE_KRM_RX_ANA_CTL(P) ((P == 0) ? (0x5A00) : (0x9A00)) #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
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#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
#define IXGBE_KX4_LINK_CNTL_1 0x4C
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX (1 << 16)
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 (1 << 17)
#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX (1 << 24)
#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 (1 << 25)
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE (1 << 29)
#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP (1 << 30)
#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART (1 << 31)
#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20
#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) #define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
#define IXGBE_SB_IOSF_TARGET_KR_PHY 0 #define IXGBE_SB_IOSF_TARGET_KR_PHY 0
#define IXGBE_SB_IOSF_TARGET_KX4_PHY 1
#define IXGBE_SB_IOSF_TARGET_KX4_PCS 2
#define IXGBE_NW_MNG_IF_SEL 0x00011178 #define IXGBE_NW_MNG_IF_SEL 0x00011178
#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)
#endif /* _IXGBE_TYPE_H_ */ #endif /* _IXGBE_TYPE_H_ */