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stable/10/sys/dev/ixgbe/ixgbe_common.c
Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines | |||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
* Initialize the function pointers. | * Initialize the function pointers. | ||||
**/ | **/ | ||||
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) | s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) | ||||
{ | { | ||||
struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | ||||
struct ixgbe_mac_info *mac = &hw->mac; | struct ixgbe_mac_info *mac = &hw->mac; | ||||
u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); | u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
DEBUGFUNC("ixgbe_init_ops_generic"); | DEBUGFUNC("ixgbe_init_ops_generic"); | ||||
/* EEPROM */ | /* EEPROM */ | ||||
eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; | eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; | ||||
/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ | /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ | ||||
if (eec & IXGBE_EEC_PRES) { | if (eec & IXGBE_EEC_PRES) { | ||||
eeprom->ops.read = ixgbe_read_eerd_generic; | eeprom->ops.read = ixgbe_read_eerd_generic; | ||||
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines | bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) | ||||
case ixgbe_media_type_copper: | case ixgbe_media_type_copper: | ||||
/* only some copper devices support flow control autoneg */ | /* only some copper devices support flow control autoneg */ | ||||
switch (hw->device_id) { | switch (hw->device_id) { | ||||
case IXGBE_DEV_ID_82599_T3_LOM: | case IXGBE_DEV_ID_82599_T3_LOM: | ||||
case IXGBE_DEV_ID_X540T: | case IXGBE_DEV_ID_X540T: | ||||
case IXGBE_DEV_ID_X540T1: | case IXGBE_DEV_ID_X540T1: | ||||
case IXGBE_DEV_ID_X540_BYPASS: | case IXGBE_DEV_ID_X540_BYPASS: | ||||
case IXGBE_DEV_ID_X550T: | case IXGBE_DEV_ID_X550T: | ||||
case IXGBE_DEV_ID_X550T1: | |||||
case IXGBE_DEV_ID_X550EM_X_10G_T: | case IXGBE_DEV_ID_X550EM_X_10G_T: | ||||
supported = TRUE; | supported = TRUE; | ||||
break; | break; | ||||
default: | default: | ||||
supported = FALSE; | supported = FALSE; | ||||
} | } | ||||
default: | default: | ||||
break; | break; | ||||
▲ Show 20 Lines • Show All 834 Lines • ▼ Show 20 Lines | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) | ||||
DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); | DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); | ||||
reg = IXGBE_READ_REG(hw, IXGBE_STATUS); | reg = IXGBE_READ_REG(hw, IXGBE_STATUS); | ||||
bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; | bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; | ||||
bus->lan_id = bus->func; | bus->lan_id = bus->func; | ||||
/* check for a port swap */ | /* check for a port swap */ | ||||
reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); | reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); | ||||
if (reg & IXGBE_FACTPS_LFS) | if (reg & IXGBE_FACTPS_LFS) | ||||
bus->func ^= 0x1; | bus->func ^= 0x1; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_stop_adapter_generic - Generic stop Tx/Rx units | * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | if (eeprom->type == ixgbe_eeprom_uninitialized) { | ||||
eeprom->semaphore_delay = 10; | eeprom->semaphore_delay = 10; | ||||
/* Clear EEPROM page size, it will be initialized as needed */ | /* Clear EEPROM page size, it will be initialized as needed */ | ||||
eeprom->word_page_size = 0; | eeprom->word_page_size = 0; | ||||
/* | /* | ||||
* Check for EEPROM present first. | * Check for EEPROM present first. | ||||
* If not present leave as none | * If not present leave as none | ||||
*/ | */ | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
if (eec & IXGBE_EEC_PRES) { | if (eec & IXGBE_EEC_PRES) { | ||||
eeprom->type = ixgbe_eeprom_spi; | eeprom->type = ixgbe_eeprom_spi; | ||||
/* | /* | ||||
* SPI EEPROM is assumed here. This code would need to | * SPI EEPROM is assumed here. This code would need to | ||||
* change if a future EEPROM is not SPI. | * change if a future EEPROM is not SPI. | ||||
*/ | */ | ||||
eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | ||||
▲ Show 20 Lines • Show All 544 Lines • ▼ Show 20 Lines | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) | ||||
DEBUGFUNC("ixgbe_acquire_eeprom"); | DEBUGFUNC("ixgbe_acquire_eeprom"); | ||||
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) | ||||
!= IXGBE_SUCCESS) | != IXGBE_SUCCESS) | ||||
status = IXGBE_ERR_SWFW_SYNC; | status = IXGBE_ERR_SWFW_SYNC; | ||||
if (status == IXGBE_SUCCESS) { | if (status == IXGBE_SUCCESS) { | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
/* Request EEPROM Access */ | /* Request EEPROM Access */ | ||||
eec |= IXGBE_EEC_REQ; | eec |= IXGBE_EEC_REQ; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { | for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
if (eec & IXGBE_EEC_GNT) | if (eec & IXGBE_EEC_GNT) | ||||
break; | break; | ||||
usec_delay(5); | usec_delay(5); | ||||
} | } | ||||
/* Release if grant not acquired */ | /* Release if grant not acquired */ | ||||
if (!(eec & IXGBE_EEC_GNT)) { | if (!(eec & IXGBE_EEC_GNT)) { | ||||
eec &= ~IXGBE_EEC_REQ; | eec &= ~IXGBE_EEC_REQ; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
DEBUGOUT("Could not acquire EEPROM grant\n"); | DEBUGOUT("Could not acquire EEPROM grant\n"); | ||||
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | ||||
status = IXGBE_ERR_EEPROM; | status = IXGBE_ERR_EEPROM; | ||||
} | } | ||||
/* Setup EEPROM for Read/Write */ | /* Setup EEPROM for Read/Write */ | ||||
if (status == IXGBE_SUCCESS) { | if (status == IXGBE_SUCCESS) { | ||||
/* Clear CS and SK */ | /* Clear CS and SK */ | ||||
eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); | eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
} | } | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
Show All 13 Lines | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) | ||||
/* Get SMBI software semaphore between device drivers first */ | /* Get SMBI software semaphore between device drivers first */ | ||||
for (i = 0; i < timeout; i++) { | for (i = 0; i < timeout; i++) { | ||||
/* | /* | ||||
* If the SMBI bit is 0 when we read it, then the bit will be | * If the SMBI bit is 0 when we read it, then the bit will be | ||||
* set and we have the semaphore | * set and we have the semaphore | ||||
*/ | */ | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
if (!(swsm & IXGBE_SWSM_SMBI)) { | if (!(swsm & IXGBE_SWSM_SMBI)) { | ||||
status = IXGBE_SUCCESS; | status = IXGBE_SUCCESS; | ||||
break; | break; | ||||
} | } | ||||
usec_delay(50); | usec_delay(50); | ||||
} | } | ||||
if (i == timeout) { | if (i == timeout) { | ||||
DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " | DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " | ||||
"not granted.\n"); | "not granted.\n"); | ||||
/* | /* | ||||
* this release is particularly important because our attempts | * this release is particularly important because our attempts | ||||
* above to get the semaphore may have succeeded, and if there | * above to get the semaphore may have succeeded, and if there | ||||
* was a timeout, we should unconditionally clear the semaphore | * was a timeout, we should unconditionally clear the semaphore | ||||
* bits to free the driver to make progress | * bits to free the driver to make progress | ||||
*/ | */ | ||||
ixgbe_release_eeprom_semaphore(hw); | ixgbe_release_eeprom_semaphore(hw); | ||||
usec_delay(50); | usec_delay(50); | ||||
/* | /* | ||||
* one last try | * one last try | ||||
* If the SMBI bit is 0 when we read it, then the bit will be | * If the SMBI bit is 0 when we read it, then the bit will be | ||||
* set and we have the semaphore | * set and we have the semaphore | ||||
*/ | */ | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
if (!(swsm & IXGBE_SWSM_SMBI)) | if (!(swsm & IXGBE_SWSM_SMBI)) | ||||
status = IXGBE_SUCCESS; | status = IXGBE_SUCCESS; | ||||
} | } | ||||
/* Now get the semaphore between SW/FW through the SWESMBI bit */ | /* Now get the semaphore between SW/FW through the SWESMBI bit */ | ||||
if (status == IXGBE_SUCCESS) { | if (status == IXGBE_SUCCESS) { | ||||
for (i = 0; i < timeout; i++) { | for (i = 0; i < timeout; i++) { | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
/* Set the SW EEPROM semaphore bit to request access */ | /* Set the SW EEPROM semaphore bit to request access */ | ||||
swsm |= IXGBE_SWSM_SWESMBI; | swsm |= IXGBE_SWSM_SWESMBI; | ||||
IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); | ||||
/* | /* | ||||
* If we set the bit successfully then we got the | * If we set the bit successfully then we got the | ||||
* semaphore. | * semaphore. | ||||
*/ | */ | ||||
swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); | ||||
if (swsm & IXGBE_SWSM_SWESMBI) | if (swsm & IXGBE_SWSM_SWESMBI) | ||||
break; | break; | ||||
usec_delay(50); | usec_delay(50); | ||||
} | } | ||||
/* | /* | ||||
* Release semaphores and return error if SW EEPROM semaphore | * Release semaphores and return error if SW EEPROM semaphore | ||||
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines | |||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
**/ | **/ | ||||
static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 eec; | u32 eec; | ||||
DEBUGFUNC("ixgbe_standby_eeprom"); | DEBUGFUNC("ixgbe_standby_eeprom"); | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
/* Toggle CS to flush commands */ | /* Toggle CS to flush commands */ | ||||
eec |= IXGBE_EEC_CS; | eec |= IXGBE_EEC_CS; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
eec &= ~IXGBE_EEC_CS; | eec &= ~IXGBE_EEC_CS; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. | * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @data: data to send to the EEPROM | * @data: data to send to the EEPROM | ||||
* @count: number of bits to shift out | * @count: number of bits to shift out | ||||
**/ | **/ | ||||
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | ||||
u16 count) | u16 count) | ||||
{ | { | ||||
u32 eec; | u32 eec; | ||||
u32 mask; | u32 mask; | ||||
u32 i; | u32 i; | ||||
DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); | DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
/* | /* | ||||
* Mask is used to shift "count" bits of "data" out to the EEPROM | * Mask is used to shift "count" bits of "data" out to the EEPROM | ||||
* one bit at a time. Determine the starting bit based on count | * one bit at a time. Determine the starting bit based on count | ||||
*/ | */ | ||||
mask = 0x01 << (count - 1); | mask = 0x01 << (count - 1); | ||||
for (i = 0; i < count; i++) { | for (i = 0; i < count; i++) { | ||||
/* | /* | ||||
* A "1" is shifted out to the EEPROM by setting bit "DI" to a | * A "1" is shifted out to the EEPROM by setting bit "DI" to a | ||||
* "1", and then raising and then lowering the clock (the SK | * "1", and then raising and then lowering the clock (the SK | ||||
* bit controls the clock input to the EEPROM). A "0" is | * bit controls the clock input to the EEPROM). A "0" is | ||||
* shifted out to the EEPROM by setting "DI" to "0" and then | * shifted out to the EEPROM by setting "DI" to "0" and then | ||||
* raising and then lowering the clock. | * raising and then lowering the clock. | ||||
*/ | */ | ||||
if (data & mask) | if (data & mask) | ||||
eec |= IXGBE_EEC_DI; | eec |= IXGBE_EEC_DI; | ||||
else | else | ||||
eec &= ~IXGBE_EEC_DI; | eec &= ~IXGBE_EEC_DI; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
ixgbe_raise_eeprom_clk(hw, &eec); | ixgbe_raise_eeprom_clk(hw, &eec); | ||||
ixgbe_lower_eeprom_clk(hw, &eec); | ixgbe_lower_eeprom_clk(hw, &eec); | ||||
/* | /* | ||||
* Shift mask to signify next bit of data to shift in to the | * Shift mask to signify next bit of data to shift in to the | ||||
* EEPROM | * EEPROM | ||||
*/ | */ | ||||
mask = mask >> 1; | mask = mask >> 1; | ||||
}; | }; | ||||
/* We leave the "DI" bit set to "0" when we leave this routine. */ | /* We leave the "DI" bit set to "0" when we leave this routine. */ | ||||
eec &= ~IXGBE_EEC_DI; | eec &= ~IXGBE_EEC_DI; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM | * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
**/ | **/ | ||||
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) | ||||
{ | { | ||||
u32 eec; | u32 eec; | ||||
u32 i; | u32 i; | ||||
u16 data = 0; | u16 data = 0; | ||||
DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); | DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); | ||||
/* | /* | ||||
* In order to read a register from the EEPROM, we need to shift | * In order to read a register from the EEPROM, we need to shift | ||||
* 'count' bits in from the EEPROM. Bits are "shifted in" by raising | * 'count' bits in from the EEPROM. Bits are "shifted in" by raising | ||||
* the clock input to the EEPROM (setting the SK bit), and then reading | * the clock input to the EEPROM (setting the SK bit), and then reading | ||||
* the value of the "DO" bit. During this "shifting in" process the | * the value of the "DO" bit. During this "shifting in" process the | ||||
* "DI" bit should always be clear. | * "DI" bit should always be clear. | ||||
*/ | */ | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); | eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); | ||||
for (i = 0; i < count; i++) { | for (i = 0; i < count; i++) { | ||||
data = data << 1; | data = data << 1; | ||||
ixgbe_raise_eeprom_clk(hw, &eec); | ixgbe_raise_eeprom_clk(hw, &eec); | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
eec &= ~(IXGBE_EEC_DI); | eec &= ~(IXGBE_EEC_DI); | ||||
if (eec & IXGBE_EEC_DO) | if (eec & IXGBE_EEC_DO) | ||||
data |= 1; | data |= 1; | ||||
ixgbe_lower_eeprom_clk(hw, &eec); | ixgbe_lower_eeprom_clk(hw, &eec); | ||||
} | } | ||||
Show All 9 Lines | |||||
{ | { | ||||
DEBUGFUNC("ixgbe_raise_eeprom_clk"); | DEBUGFUNC("ixgbe_raise_eeprom_clk"); | ||||
/* | /* | ||||
* Raise the clock input to the EEPROM | * Raise the clock input to the EEPROM | ||||
* (setting the SK bit), then delay | * (setting the SK bit), then delay | ||||
*/ | */ | ||||
*eec = *eec | IXGBE_EEC_SK; | *eec = *eec | IXGBE_EEC_SK; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. | * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @eecd: EECD's current value | * @eecd: EECD's current value | ||||
**/ | **/ | ||||
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | ||||
{ | { | ||||
DEBUGFUNC("ixgbe_lower_eeprom_clk"); | DEBUGFUNC("ixgbe_lower_eeprom_clk"); | ||||
/* | /* | ||||
* Lower the clock input to the EEPROM (clearing the SK bit), then | * Lower the clock input to the EEPROM (clearing the SK bit), then | ||||
* delay | * delay | ||||
*/ | */ | ||||
*eec = *eec & ~IXGBE_EEC_SK; | *eec = *eec & ~IXGBE_EEC_SK; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_release_eeprom - Release EEPROM, release semaphores | * ixgbe_release_eeprom - Release EEPROM, release semaphores | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
**/ | **/ | ||||
static void ixgbe_release_eeprom(struct ixgbe_hw *hw) | static void ixgbe_release_eeprom(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 eec; | u32 eec; | ||||
DEBUGFUNC("ixgbe_release_eeprom"); | DEBUGFUNC("ixgbe_release_eeprom"); | ||||
eec = IXGBE_READ_REG(hw, IXGBE_EEC); | eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); | ||||
eec |= IXGBE_EEC_CS; /* Pull CS high */ | eec |= IXGBE_EEC_CS; /* Pull CS high */ | ||||
eec &= ~IXGBE_EEC_SK; /* Lower SCK */ | eec &= ~IXGBE_EEC_SK; /* Lower SCK */ | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
usec_delay(1); | usec_delay(1); | ||||
/* Stop requesting EEPROM access */ | /* Stop requesting EEPROM access */ | ||||
eec &= ~IXGBE_EEC_REQ; | eec &= ~IXGBE_EEC_REQ; | ||||
IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); | ||||
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | ||||
/* Delay before attempt to obtain semaphore again to allow FW access */ | /* Delay before attempt to obtain semaphore again to allow FW access */ | ||||
msec_delay(hw->eeprom.semaphore_delay); | msec_delay(hw->eeprom.semaphore_delay); | ||||
} | } | ||||
/** | /** | ||||
▲ Show 20 Lines • Show All 1,039 Lines • ▼ Show 20 Lines | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) | ||||
* of this need. The first reset prevents new master requests from | * of this need. The first reset prevents new master requests from | ||||
* being issued by our device. We then must wait 1usec or more for any | * being issued by our device. We then must wait 1usec or more for any | ||||
* remaining completions from the PCIe bus to trickle in, and then reset | * remaining completions from the PCIe bus to trickle in, and then reset | ||||
* again to clear out any effects they may have had on our device. | * again to clear out any effects they may have had on our device. | ||||
*/ | */ | ||||
DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); | DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); | ||||
hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | ||||
if (hw->mac.type >= ixgbe_mac_X550) | |||||
goto out; | |||||
/* | /* | ||||
* Before proceeding, make sure that the PCIe block does not have | * Before proceeding, make sure that the PCIe block does not have | ||||
* transactions pending. | * transactions pending. | ||||
*/ | */ | ||||
poll = ixgbe_pcie_timeout_poll(hw); | poll = ixgbe_pcie_timeout_poll(hw); | ||||
for (i = 0; i < poll; i++) { | for (i = 0; i < poll; i++) { | ||||
usec_delay(100); | usec_delay(100); | ||||
value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); | value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); | ||||
▲ Show 20 Lines • Show All 906 Lines • ▼ Show 20 Lines | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | ||||
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | ||||
if (links_orig != links_reg) { | if (links_orig != links_reg) { | ||||
DEBUGOUT2("LINKS changed from %08X to %08X\n", | DEBUGOUT2("LINKS changed from %08X to %08X\n", | ||||
links_orig, links_reg); | links_orig, links_reg); | ||||
} | } | ||||
if (link_up_wait_to_complete) { | if (link_up_wait_to_complete) { | ||||
for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | for (i = 0; i < hw->mac.max_link_up_time; i++) { | ||||
if (links_reg & IXGBE_LINKS_UP) { | if (links_reg & IXGBE_LINKS_UP) { | ||||
*link_up = TRUE; | *link_up = TRUE; | ||||
break; | break; | ||||
} else { | } else { | ||||
*link_up = FALSE; | *link_up = FALSE; | ||||
} | } | ||||
msec_delay(100); | msec_delay(100); | ||||
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | ||||
▲ Show 20 Lines • Show All 629 Lines • ▼ Show 20 Lines | |||||
*/ | */ | ||||
bool ixgbe_mng_present(struct ixgbe_hw *hw) | bool ixgbe_mng_present(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 fwsm; | u32 fwsm; | ||||
if (hw->mac.type < ixgbe_mac_82599EB) | if (hw->mac.type < ixgbe_mac_82599EB) | ||||
return FALSE; | return FALSE; | ||||
fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); | fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); | ||||
fwsm &= IXGBE_FWSM_MODE_MASK; | fwsm &= IXGBE_FWSM_MODE_MASK; | ||||
return fwsm == IXGBE_FWSM_FW_MODE_PT; | return fwsm == IXGBE_FWSM_FW_MODE_PT; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_mng_enabled - Is the manageability engine enabled? | * ixgbe_mng_enabled - Is the manageability engine enabled? | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
* Returns TRUE if the manageability engine is enabled. | * Returns TRUE if the manageability engine is enabled. | ||||
**/ | **/ | ||||
bool ixgbe_mng_enabled(struct ixgbe_hw *hw) | bool ixgbe_mng_enabled(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 fwsm, manc, factps; | u32 fwsm, manc, factps; | ||||
fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); | fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); | ||||
if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) | if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) | ||||
return FALSE; | return FALSE; | ||||
manc = IXGBE_READ_REG(hw, IXGBE_MANC); | manc = IXGBE_READ_REG(hw, IXGBE_MANC); | ||||
if (!(manc & IXGBE_MANC_RCV_TCO_EN)) | if (!(manc & IXGBE_MANC_RCV_TCO_EN)) | ||||
return FALSE; | return FALSE; | ||||
if (hw->mac.type <= ixgbe_mac_X540) { | if (hw->mac.type <= ixgbe_mac_X540) { | ||||
factps = IXGBE_READ_REG(hw, IXGBE_FACTPS); | factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); | ||||
if (factps & IXGBE_FACTPS_MNGCG) | if (factps & IXGBE_FACTPS_MNGCG) | ||||
return FALSE; | return FALSE; | ||||
} | } | ||||
return TRUE; | return TRUE; | ||||
} | } | ||||
/** | /** | ||||
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