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Differential D5117 Diff 13233 stable/10/sys/dev/ixgbe/ixgbe_82599.c

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stable/10/sys/dev/ixgbe/ixgbe_82599.c

Show First 20 Lines • Show All 376 Lines • ▼ Show 20 Liness32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; & IXGBE_FWSM_MODE_MASK);
hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
/* EEPROM */ /* EEPROM */
eeprom->ops.read = ixgbe_read_eeprom_82599; eeprom->ops.read = ixgbe_read_eeprom_82599;
eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
/* Manageability interface */ /* Manageability interface */
▲ Show 20 Lines • Show All 970 Lines • ▼ Show 20 Liness32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
bool cloud_mode) bool cloud_mode)
{ {
DEBUGFUNC("ixgbe_init_fdir_perfect_82599"); DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
/* /*
* Continue setup of fdirctrl register bits: * Continue setup of fdirctrl register bits:
* Turn perfect match filtering on * Turn perfect match filtering on
* Report hash in RSS field of Rx wb descriptor * Report hash in RSS field of Rx wb descriptor
* Initialize the drop queue * Initialize the drop queue to queue 127
* Move the flexible bytes to use the ethertype - shift 6 words * Move the flexible bytes to use the ethertype - shift 6 words
* Set the maximum length per hash bucket to 0xA filters * Set the maximum length per hash bucket to 0xA filters
* Send interrupt when 64 (0x4 * 16) filters are left * Send interrupt when 64 (0x4 * 16) filters are left
*/ */
fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
IXGBE_FDIRCTRL_REPORT_STATUS | IXGBE_FDIRCTRL_REPORT_STATUS |
(IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
(0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
if ((hw->mac.type == ixgbe_mac_X550) ||
(hw->mac.type == ixgbe_mac_X550EM_x))
fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
if (cloud_mode) if (cloud_mode)
fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD << fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
IXGBE_FDIRCTRL_FILTERMODE_SHIFT); IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
/* write hashes and fdirctrl register, poll for completion */ /* write hashes and fdirctrl register, poll for completion */
ixgbe_fdir_enable_82599(hw, fdirctrl); ixgbe_fdir_enable_82599(hw, fdirctrl);
return IXGBE_SUCCESS; return IXGBE_SUCCESS;
} }
/**
* ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
* @hw: pointer to hardware structure
* @dropqueue: Rx queue index used for the dropped packets
**/
void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
{
u32 fdirctrl;
DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
/* Clear init done bit and drop queue field */
fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
/* Set drop queue */
fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
if ((hw->mac.type == ixgbe_mac_X550) ||
(hw->mac.type == ixgbe_mac_X550EM_x))
fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
IXGBE_FDIRCMD_CLEARHT));
IXGBE_WRITE_FLUSH(hw);
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
~IXGBE_FDIRCMD_CLEARHT));
IXGBE_WRITE_FLUSH(hw);
/* write hashes and fdirctrl register, poll for completion */
ixgbe_fdir_enable_82599(hw, fdirctrl);
}
/* /*
* These defines allow us to quickly generate all of the necessary instructions * These defines allow us to quickly generate all of the necessary instructions
* in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
* for values 0 through 15 * for values 0 through 15
*/ */
#define IXGBE_ATR_COMMON_HASH_KEY \ #define IXGBE_ATR_COMMON_HASH_KEY \
(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @input: unique input dword * @input: unique input dword
* @common: compressed common input dword * @common: compressed common input dword
* @queue: queue index to direct traffic to * @queue: queue index to direct traffic to
* *
* Note that the tunnel bit in input must not be set when the hardware * Note that the tunnel bit in input must not be set when the hardware
* tunneling support does not exist. * tunneling support does not exist.
**/ **/
s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_hash_dword input, union ixgbe_atr_hash_dword input,
union ixgbe_atr_hash_dword common, union ixgbe_atr_hash_dword common,
u8 queue) u8 queue)
{ {
u64 fdirhashcmd; u64 fdirhashcmd;
u8 flow_type; u8 flow_type;
bool tunnel; bool tunnel;
u32 fdircmd; u32 fdircmd;
s32 err;
DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599"); DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
/* /*
* Get the flow_type in order to program FDIRCMD properly * Get the flow_type in order to program FDIRCMD properly
* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
* fifth is FDIRCMD.TUNNEL_FILTER * fifth is FDIRCMD.TUNNEL_FILTER
*/ */
tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
flow_type = input.formatted.flow_type & flow_type = input.formatted.flow_type &
(IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
switch (flow_type) { switch (flow_type) {
case IXGBE_ATR_FLOW_TYPE_TCPV4: case IXGBE_ATR_FLOW_TYPE_TCPV4:
case IXGBE_ATR_FLOW_TYPE_UDPV4: case IXGBE_ATR_FLOW_TYPE_UDPV4:
case IXGBE_ATR_FLOW_TYPE_SCTPV4: case IXGBE_ATR_FLOW_TYPE_SCTPV4:
case IXGBE_ATR_FLOW_TYPE_TCPV6: case IXGBE_ATR_FLOW_TYPE_TCPV6:
case IXGBE_ATR_FLOW_TYPE_UDPV6: case IXGBE_ATR_FLOW_TYPE_UDPV6:
case IXGBE_ATR_FLOW_TYPE_SCTPV6: case IXGBE_ATR_FLOW_TYPE_SCTPV6:
break; break;
default: default:
DEBUGOUT(" Error on flow type input\n"); DEBUGOUT(" Error on flow type input\n");
return IXGBE_ERR_CONFIG; return;
} }
/* configure FDIRCMD register */ /* configure FDIRCMD register */
fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
if (tunnel) if (tunnel)
fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
/* /*
* The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
* is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
*/ */
fdirhashcmd = (u64)fdircmd << 32; fdirhashcmd = (u64)fdircmd << 32;
fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
if (err) {
DEBUGOUT("Flow Director command did not complete!\n");
return err;
}
DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
return IXGBE_SUCCESS; return;
} }
#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
do { \ do { \
u32 n = (_n); \ u32 n = (_n); \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
bucket_hash ^= lo_hash_dword >> n; \ bucket_hash ^= lo_hash_dword >> n; \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
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