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sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
| /* SPDX-License-Identifier: BSD-3-Clause */ | /* SPDX-License-Identifier: BSD-3-Clause */ | ||||
| /* Copyright(c) 2007-2022 Intel Corporation */ | /* Copyright(c) 2007-2022 Intel Corporation */ | ||||
| /* $FreeBSD$ */ | /* $FreeBSD$ */ | ||||
| #include <linux/atomic.h> | #include <linux/atomic.h> | ||||
| #include <linux/compiler.h> | #include <linux/compiler.h> | ||||
| #include <adf_accel_devices.h> | #include <adf_accel_devices.h> | ||||
| #include <adf_common_drv.h> | #include <adf_common_drv.h> | ||||
| #include <adf_pf2vf_msg.h> | #include <adf_pf2vf_msg.h> | ||||
| #include <adf_dev_err.h> | #include <adf_dev_err.h> | ||||
| #include <adf_cfg.h> | #include <adf_cfg.h> | ||||
| #include <adf_fw_counters.h> | #include <adf_fw_counters.h> | ||||
| #include <adf_gen2_hw_data.h> | |||||
| #include "adf_c4xxx_hw_data.h" | #include "adf_c4xxx_hw_data.h" | ||||
| #include "adf_c4xxx_reset.h" | #include "adf_c4xxx_reset.h" | ||||
| #include "adf_c4xxx_inline.h" | #include "adf_c4xxx_inline.h" | ||||
| #include "adf_c4xxx_ras.h" | #include "adf_c4xxx_ras.h" | ||||
| #include "adf_c4xxx_misc_error_stats.h" | #include "adf_c4xxx_misc_error_stats.h" | ||||
| #include "adf_c4xxx_pke_replay_stats.h" | #include "adf_c4xxx_pke_replay_stats.h" | ||||
| #include "adf_heartbeat.h" | #include "adf_heartbeat.h" | ||||
| #include "icp_qat_fw_init_admin.h" | #include "icp_qat_fw_init_admin.h" | ||||
| ▲ Show 20 Lines • Show All 729 Lines • ▼ Show 20 Lines | capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC | | ||||
| ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC | | ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC | | ||||
| ICP_ACCEL_CAPABILITIES_CIPHER | | ICP_ACCEL_CAPABILITIES_CIPHER | | ||||
| ICP_ACCEL_CAPABILITIES_AUTHENTICATION | | ICP_ACCEL_CAPABILITIES_AUTHENTICATION | | ||||
| ICP_ACCEL_CAPABILITIES_COMPRESSION | ICP_ACCEL_CAPABILITIES_ZUC | | ICP_ACCEL_CAPABILITIES_COMPRESSION | ICP_ACCEL_CAPABILITIES_ZUC | | ||||
| ICP_ACCEL_CAPABILITIES_HKDF | ICP_ACCEL_CAPABILITIES_SHA3_EXT | | ICP_ACCEL_CAPABILITIES_HKDF | ICP_ACCEL_CAPABILITIES_SHA3_EXT | | ||||
| ICP_ACCEL_CAPABILITIES_SM3 | ICP_ACCEL_CAPABILITIES_SM4 | | ICP_ACCEL_CAPABILITIES_SM3 | ICP_ACCEL_CAPABILITIES_SM4 | | ||||
| ICP_ACCEL_CAPABILITIES_CHACHA_POLY | | ICP_ACCEL_CAPABILITIES_CHACHA_POLY | | ||||
| ICP_ACCEL_CAPABILITIES_AESGCM_SPC | | ICP_ACCEL_CAPABILITIES_AESGCM_SPC | | ||||
| ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY | | |||||
| ICP_ACCEL_CAPABILITIES_ECEDMONT; | ICP_ACCEL_CAPABILITIES_ECEDMONT; | ||||
| if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE) { | if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE) { | ||||
| capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC; | capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC; | ||||
| capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER; | capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER; | ||||
| } | } | ||||
| if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE) | if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE) | ||||
| capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION; | capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION; | ||||
| ▲ Show 20 Lines • Show All 1,357 Lines • ▼ Show 20 Lines | for (i = 0; i < ADF_C4XXX_AE2FUNC_REG_PER_AE * num_aes; i++) { | ||||
| else | else | ||||
| reg &= ~ADF_C4XXX_AE2FUNC_MAP_VALID; | reg &= ~ADF_C4XXX_AE2FUNC_MAP_VALID; | ||||
| ADF_CSR_WR(addr + ADF_C4XXX_AE2FUNC_MAP_OFFSET, | ADF_CSR_WR(addr + ADF_C4XXX_AE2FUNC_MAP_OFFSET, | ||||
| i * ADF_C4XXX_AE2FUNC_MAP_REG_SIZE, | i * ADF_C4XXX_AE2FUNC_MAP_REG_SIZE, | ||||
| reg); | reg); | ||||
| } | } | ||||
| } | } | ||||
| static int | |||||
| adf_get_heartbeat_status_c4xxx(struct adf_accel_dev *accel_dev) | |||||
| { | |||||
| struct adf_hw_device_data *hw_device = accel_dev->hw_device; | |||||
| struct icp_qat_fw_init_c4xxx_admin_hb_stats *live_s = | |||||
| (struct icp_qat_fw_init_c4xxx_admin_hb_stats *) | |||||
| accel_dev->admin->virt_hb_addr; | |||||
| const size_t max_aes = hw_device->get_num_aes(hw_device); | |||||
| const size_t stats_size = | |||||
| max_aes * sizeof(struct icp_qat_fw_init_c4xxx_admin_hb_stats); | |||||
| int ret = 0; | |||||
| size_t ae = 0, thr; | |||||
| unsigned long ae_mask = 0; | |||||
| int num_threads_per_ae = ADF_NUM_THREADS_PER_AE; | |||||
| /* | |||||
| * Memory layout of Heartbeat | |||||
| * | |||||
| * +----------------+----------------+---------+ | |||||
| * | Live value | Last value | Count | | |||||
| * +----------------+----------------+---------+ | |||||
| * \_______________/\_______________/\________/ | |||||
| * ^ ^ ^ | |||||
| * | | | | |||||
| * | | max_aes * sizeof(adf_hb_count) | |||||
| * | max_aes * | |||||
| * sizeof(icp_qat_fw_init_c4xxx_admin_hb_stats) | |||||
| * max_aes * sizeof(icp_qat_fw_init_c4xxx_admin_hb_stats) | |||||
| */ | |||||
| struct icp_qat_fw_init_c4xxx_admin_hb_stats *curr_s; | |||||
| struct icp_qat_fw_init_c4xxx_admin_hb_stats *last_s = live_s + max_aes; | |||||
| struct adf_hb_count *count = (struct adf_hb_count *)(last_s + max_aes); | |||||
| curr_s = malloc(stats_size, M_QAT, M_WAITOK | M_ZERO); | |||||
| memcpy(curr_s, live_s, stats_size); | |||||
| ae_mask = hw_device->ae_mask; | |||||
| for_each_set_bit(ae, &ae_mask, max_aes) | |||||
| { | |||||
| for (thr = 0; thr < num_threads_per_ae; ++thr) { | |||||
| struct icp_qat_fw_init_admin_hb_cnt *curr = | |||||
| &curr_s[ae].stats[thr]; | |||||
| struct icp_qat_fw_init_admin_hb_cnt *prev = | |||||
| &last_s[ae].stats[thr]; | |||||
| u16 req = curr->req_heartbeat_cnt; | |||||
| u16 resp = curr->resp_heartbeat_cnt; | |||||
| u16 last = prev->resp_heartbeat_cnt; | |||||
| if ((thr == ADF_AE_ADMIN_THREAD || req != resp) && | |||||
| resp == last) { | |||||
| u16 retry = ++count[ae].ae_thread[thr]; | |||||
| if (retry >= ADF_CFG_HB_COUNT_THRESHOLD) | |||||
| ret = EIO; | |||||
| } else { | |||||
| count[ae].ae_thread[thr] = 0; | |||||
| } | |||||
| } | |||||
| } | |||||
| /* Copy current stats for the next iteration */ | |||||
| memcpy(last_s, curr_s, stats_size); | |||||
| free(curr_s, M_QAT); | |||||
| return ret; | |||||
| } | |||||
| void | void | ||||
| adf_init_hw_data_c4xxx(struct adf_hw_device_data *hw_data) | adf_init_hw_data_c4xxx(struct adf_hw_device_data *hw_data) | ||||
| { | { | ||||
| hw_data->dev_class = &c4xxx_class; | hw_data->dev_class = &c4xxx_class; | ||||
| hw_data->instance_id = c4xxx_class.instances++; | hw_data->instance_id = c4xxx_class.instances++; | ||||
| hw_data->num_banks = ADF_C4XXX_ETR_MAX_BANKS; | hw_data->num_banks = ADF_C4XXX_ETR_MAX_BANKS; | ||||
| hw_data->num_rings_per_bank = ADF_C4XXX_NUM_RINGS_PER_BANK; | hw_data->num_rings_per_bank = ADF_C4XXX_NUM_RINGS_PER_BANK; | ||||
| hw_data->num_accel = ADF_C4XXX_MAX_ACCELERATORS; | hw_data->num_accel = ADF_C4XXX_MAX_ACCELERATORS; | ||||
| Show All 18 Lines | adf_init_hw_data_c4xxx(struct adf_hw_device_data *hw_data) | ||||
| hw_data->get_pf2vf_offset = get_pf2vf_offset; | hw_data->get_pf2vf_offset = get_pf2vf_offset; | ||||
| hw_data->get_vintmsk_offset = get_vintmsk_offset; | hw_data->get_vintmsk_offset = get_vintmsk_offset; | ||||
| hw_data->get_arb_info = get_arb_info; | hw_data->get_arb_info = get_arb_info; | ||||
| hw_data->get_admin_info = get_admin_info; | hw_data->get_admin_info = get_admin_info; | ||||
| hw_data->get_errsou_offset = get_errsou_offset; | hw_data->get_errsou_offset = get_errsou_offset; | ||||
| hw_data->get_clock_speed = get_clock_speed; | hw_data->get_clock_speed = get_clock_speed; | ||||
| hw_data->get_eth_doorbell_msg = get_eth_doorbell_msg; | hw_data->get_eth_doorbell_msg = get_eth_doorbell_msg; | ||||
| hw_data->get_sku = get_sku; | hw_data->get_sku = get_sku; | ||||
| hw_data->heartbeat_ctr_num = ADF_NUM_THREADS_PER_AE; | |||||
| hw_data->check_prod_sku = c4xxx_check_prod_sku; | hw_data->check_prod_sku = c4xxx_check_prod_sku; | ||||
| hw_data->fw_name = ADF_C4XXX_FW; | hw_data->fw_name = ADF_C4XXX_FW; | ||||
| hw_data->fw_mmp_name = ADF_C4XXX_MMP; | hw_data->fw_mmp_name = ADF_C4XXX_MMP; | ||||
| hw_data->get_obj_name = get_obj_name; | hw_data->get_obj_name = get_obj_name; | ||||
| hw_data->get_objs_num = get_objs_num; | hw_data->get_objs_num = get_objs_num; | ||||
| hw_data->get_obj_cfg_ae_mask = get_obj_cfg_ae_mask; | hw_data->get_obj_cfg_ae_mask = get_obj_cfg_ae_mask; | ||||
| hw_data->init_admin_comms = adf_init_admin_comms; | hw_data->init_admin_comms = adf_init_admin_comms; | ||||
| hw_data->exit_admin_comms = adf_exit_admin_comms; | hw_data->exit_admin_comms = adf_exit_admin_comms; | ||||
| Show All 10 Lines | adf_init_hw_data_c4xxx(struct adf_hw_device_data *hw_data) | ||||
| hw_data->disable_vf2pf_comms = adf_pf_disable_vf2pf_comms; | hw_data->disable_vf2pf_comms = adf_pf_disable_vf2pf_comms; | ||||
| hw_data->reset_device = adf_reset_flr; | hw_data->reset_device = adf_reset_flr; | ||||
| hw_data->restore_device = adf_c4xxx_dev_restore; | hw_data->restore_device = adf_c4xxx_dev_restore; | ||||
| hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; | hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; | ||||
| hw_data->init_accel_units = adf_init_accel_units; | hw_data->init_accel_units = adf_init_accel_units; | ||||
| hw_data->reset_hw_units = adf_c4xxx_reset_hw_units; | hw_data->reset_hw_units = adf_c4xxx_reset_hw_units; | ||||
| hw_data->exit_accel_units = adf_exit_accel_units; | hw_data->exit_accel_units = adf_exit_accel_units; | ||||
| hw_data->ring_to_svc_map = ADF_DEFAULT_RING_TO_SRV_MAP; | hw_data->ring_to_svc_map = ADF_DEFAULT_RING_TO_SRV_MAP; | ||||
| hw_data->get_heartbeat_status = adf_get_heartbeat_status_c4xxx; | hw_data->get_heartbeat_status = adf_get_heartbeat_status; | ||||
| hw_data->get_ae_clock = get_ae_clock; | hw_data->get_ae_clock = get_ae_clock; | ||||
| hw_data->clock_frequency = ADF_C4XXX_AE_FREQ; | hw_data->clock_frequency = ADF_C4XXX_AE_FREQ; | ||||
| hw_data->measure_clock = measure_clock; | hw_data->measure_clock = measure_clock; | ||||
| hw_data->add_pke_stats = adf_pke_replay_counters_add_c4xxx; | hw_data->add_pke_stats = adf_pke_replay_counters_add_c4xxx; | ||||
| hw_data->remove_pke_stats = adf_pke_replay_counters_remove_c4xxx; | hw_data->remove_pke_stats = adf_pke_replay_counters_remove_c4xxx; | ||||
| hw_data->add_misc_error = adf_misc_error_add_c4xxx; | hw_data->add_misc_error = adf_misc_error_add_c4xxx; | ||||
| hw_data->remove_misc_error = adf_misc_error_remove_c4xxx; | hw_data->remove_misc_error = adf_misc_error_remove_c4xxx; | ||||
| hw_data->extended_dc_capabilities = 0; | hw_data->extended_dc_capabilities = 0; | ||||
| hw_data->get_storage_enabled = get_storage_enabled; | hw_data->get_storage_enabled = get_storage_enabled; | ||||
| hw_data->query_storage_cap = 0; | hw_data->query_storage_cap = 0; | ||||
| hw_data->get_accel_cap = c4xxx_get_hw_cap; | hw_data->get_accel_cap = c4xxx_get_hw_cap; | ||||
| hw_data->configure_accel_units = c4xxx_configure_accel_units; | hw_data->configure_accel_units = c4xxx_configure_accel_units; | ||||
| hw_data->pre_reset = adf_dev_pre_reset; | hw_data->pre_reset = adf_dev_pre_reset; | ||||
| hw_data->post_reset = adf_dev_post_reset; | hw_data->post_reset = adf_dev_post_reset; | ||||
| hw_data->get_ring_to_svc_map = adf_cfg_get_services_enabled; | hw_data->get_ring_to_svc_map = adf_cfg_get_services_enabled; | ||||
| hw_data->count_ras_event = adf_fw_count_ras_event; | hw_data->count_ras_event = adf_fw_count_ras_event; | ||||
| hw_data->config_device = adf_config_device; | hw_data->config_device = adf_config_device; | ||||
| hw_data->set_asym_rings_mask = adf_cfg_set_asym_rings_mask; | hw_data->set_asym_rings_mask = adf_cfg_set_asym_rings_mask; | ||||
| adf_gen2_init_hw_csr_info(&hw_data->csr_info); | |||||
| hw_data->csr_info.arb_enable_mask = 0xF; | |||||
| } | } | ||||
| void | void | ||||
| adf_clean_hw_data_c4xxx(struct adf_hw_device_data *hw_data) | adf_clean_hw_data_c4xxx(struct adf_hw_device_data *hw_data) | ||||
| { | { | ||||
| hw_data->dev_class->instances--; | hw_data->dev_class->instances--; | ||||
| } | } | ||||
| Show All 17 Lines | |||||