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Differential D36254 Diff 115177 sys/dev/qat/qat_common/adf_hw_arbiter.c

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sys/dev/qat/qat_common/adf_hw_arbiter.c

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines WRITE_CSR_ARB_WRK_2_SER_MAP(csr,
i, i,
*(thd_2_arb_cfg + i)); *(thd_2_arb_cfg + i));
return 0; return 0;
} }
void void
adf_update_ring_arb(struct adf_etr_ring_data *ring) adf_update_ring_arb(struct adf_etr_ring_data *ring)
{ {
WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr, int shift;
u32 arben, arben_tx, arben_rx, arb_mask;
struct adf_accel_dev *accel_dev = ring->bank->accel_dev;
struct adf_hw_csr_info *csr_info = &accel_dev->hw_device->csr_info;
struct adf_hw_csr_ops *csr_ops = &csr_info->csr_ops;
arb_mask = csr_info->arb_enable_mask;
shift = hweight32(arb_mask);
arben_tx = ring->bank->ring_mask & arb_mask;
arben_rx = (ring->bank->ring_mask >> shift) & arb_mask;
arben = arben_tx & arben_rx;
csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr,
ring->bank->bank_number, ring->bank->bank_number,
ring->bank->ring_mask & 0xFF); arben);
} }
void void
adf_enable_ring_arb(void *csr_addr, unsigned int bank_nr, unsigned int mask) adf_enable_ring_arb(struct adf_accel_dev *accel_dev,
void *csr_addr,
unsigned int bank_nr,
unsigned int mask)
{ {
struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
struct resource *csr = csr_addr; struct resource *csr = csr_addr;
u32 arbenable; u32 arbenable;
if (!csr) if (!csr)
return; return;
mutex_lock(&csr_arb_lock); mutex_lock(&csr_arb_lock);
arbenable = READ_CSR_ARB_RINGSRVARBEN(csr, bank_nr); arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr);
arbenable |= mask & 0xFF; arbenable |= mask & 0xFF;
WRITE_CSR_ARB_RINGSRVARBEN(csr, bank_nr, arbenable); csr_ops->write_csr_ring_srv_arb_en(csr, bank_nr, arbenable);
mutex_unlock(&csr_arb_lock); mutex_unlock(&csr_arb_lock);
} }
void void
adf_disable_ring_arb(void *csr_addr, unsigned int bank_nr, unsigned int mask) adf_disable_ring_arb(struct adf_accel_dev *accel_dev,
void *csr_addr,
unsigned int bank_nr,
unsigned int mask)
{ {
struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
struct resource *csr = csr_addr; struct resource *csr = csr_addr;
u32 arbenable; u32 arbenable;
if (!csr_addr) if (!csr_addr)
return; return;
mutex_lock(&csr_arb_lock); mutex_lock(&csr_arb_lock);
arbenable = READ_CSR_ARB_RINGSRVARBEN(csr, bank_nr); arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr);
arbenable &= ~mask & 0xFF; arbenable &= ~mask & 0xFF;
WRITE_CSR_ARB_RINGSRVARBEN(csr, bank_nr, arbenable); csr_ops->write_csr_ring_srv_arb_en(csr, bank_nr, arbenable);
mutex_unlock(&csr_arb_lock); mutex_unlock(&csr_arb_lock);
} }
void void
adf_exit_arb(struct adf_accel_dev *accel_dev) adf_exit_arb(struct adf_accel_dev *accel_dev)
{ {
struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
struct adf_hw_device_data *hw_data = accel_dev->hw_device; struct adf_hw_device_data *hw_data = accel_dev->hw_device;
struct arb_info info; struct arb_info info;
struct resource *csr; struct resource *csr;
unsigned int i; unsigned int i;
if (!accel_dev->transport) if (!accel_dev->transport)
return; return;
Show All 12 Lines for (i = 0; i < hw_data->num_engines; i++)
info.arbiter_offset, info.arbiter_offset,
info.wrk_thd_2_srv_arb_map, info.wrk_thd_2_srv_arb_map,
i, i,
0); 0);
} }
/* Disable arbitration on all rings */ /* Disable arbitration on all rings */
for (i = 0; i < GET_MAX_BANKS(accel_dev); i++) for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0); csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
} }
void void
adf_disable_arb(struct adf_accel_dev *accel_dev) adf_disable_arb(struct adf_accel_dev *accel_dev)
{ {
struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
struct resource *csr; struct resource *csr;
unsigned int i; unsigned int i;
if (!accel_dev || !accel_dev->transport) if (!accel_dev || !accel_dev->transport)
return; return;
csr = accel_dev->transport->banks[0].csr_addr; csr = accel_dev->transport->banks[0].csr_addr;
/* Disable arbitration on all rings */ /* Disable arbitration on all rings */
for (i = 0; i < GET_MAX_BANKS(accel_dev); i++) for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0); csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
} }